Patents by Inventor Tatsuji Araya
Tatsuji Araya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7936579Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: June 2, 2010Date of Patent: May 3, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Publication number: 20100238716Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: ApplicationFiled: June 2, 2010Publication date: September 23, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Patent number: 7755928Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: February 6, 2009Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Publication number: 20090154216Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: ApplicationFiled: February 6, 2009Publication date: June 18, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Patent number: 7508692Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: May 25, 2007Date of Patent: March 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Publication number: 20070223271Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: ApplicationFiled: May 25, 2007Publication date: September 27, 2007Applicant: FUJITSU LIMITEDInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Patent number: 7269053Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: November 16, 2004Date of Patent: September 11, 2007Assignee: Fujitsu LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Publication number: 20060017181Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: ApplicationFiled: November 16, 2004Publication date: January 26, 2006Applicant: FUJITSU LIMITEDInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema