Patents by Inventor Tatsuji Ashitani
Tatsuji Ashitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240019244Abstract: Shape measuring systems are disclosed. In one example, a shape measuring system includes a light source part with a light source, a waveform control lens, and a scan mechanism. It also includes light receiving parts that each include a light receiving lens on which reflected light reflected by the measurement target among measurement light from the light source part is incident, an EVS, which is an asynchronous imaging device that is a light receiving element, an event issuing part that detects an event on the basis of output data from the EVS and outputs event data, and a transmitting part that outputs the event data to the signal processing part. A signal processing part includes an unwanted signal removing part that removes an unwanted signal resulting from incidence of secondary reflected light, and a three-dimensional calculating part that calculates a three-dimensional shape of the measurement target.Type: ApplicationFiled: October 8, 2021Publication date: January 18, 2024Inventors: Yoshitaka Miyatani, Tatsuji Ashitani, Ryuta Okamoto
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Patent number: 11477406Abstract: An imaging device according to the present disclosure includes a plurality of pixel units each including a first pixel unit and a second pixel unit and a vertical signal line, in which each of the first pixel unit and the second pixel unit includes an amplification transistor, a selection transistor connected between the amplification transistor and the vertical signal line, and a connection unit that selectively connects between a common connection node of the amplification transistor and the selection transistor of the first pixel unit and a common connection node of the amplification transistor and the selection transistor of the second pixel unit.Type: GrantFiled: December 18, 2018Date of Patent: October 18, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Tatsuji Ashitani, Yukiyasu Tatsuzawa
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Publication number: 20210067726Abstract: An imaging device according to the present disclosure includes a plurality of pixel units each including a first pixel unit and a second pixel unit and a vertical signal line, in which each of the first pixel unit and the second pixel unit includes an amplification transistor, a selection transistor connected between the amplification transistor and the vertical signal line, and a connection unit that selectively connects between a common connection node of the amplification transistor and the selection transistor of the first pixel unit and a common connection node of the amplification transistor and the selection transistor of the second pixel unit.Type: ApplicationFiled: December 18, 2018Publication date: March 4, 2021Inventors: TATSUJI ASHITANI, YUKIYASU TATSUZAWA
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Publication number: 20160205335Abstract: According to one embodiment, a solid-state imaging device includes a pixel array, a scanning circuit, signal lines, processing circuits, and connection parts. One processing circuit and the signal lines are provided per one pixel column of the pixel array. The signal lines include a first signal line and a second signal line. Each pixel column includes first pixels and second pixels. The first pixels are configured to output pixel signals to the first signal line. The second pixels are configured to output pixel signals to the second signal line. When the scanning circuit simultaneously selects a first pixel row and a second pixel row, the connection parts connect the first signal line and the second signal line of each pixel column to different processing circuits. The first pixel row includes the first pixels. The second pixel row includes the second pixels.Type: ApplicationFiled: May 20, 2015Publication date: July 14, 2016Inventors: Kazuhiro HIWADA, Yukiyasu TATSUZAWA, Tatsuji ASHITANI
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Publication number: 20150365638Abstract: According to one embodiment, a signal processing circuit includes a defect correction circuit. The defect correction circuit includes a color difference calculation part, a color difference sorting part, and a correction amount calculation part. The color difference calculation part is configured to calculate a difference between a signal level of a first pixel and a signal level of a second pixel in a pixel group. The pixel group includes pixels juxtaposed in a horizontal direction with a target pixel at a center. The correction amount calculation part is configured to calculate a correction amount for the target pixel, based on a difference chosen by the color difference sorting part and a signal level of a second pixel adjacent to the target pixel.Type: ApplicationFiled: March 2, 2015Publication date: December 17, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yukiyasu TATSUZAWA, Tatsuji Ashitani, Kazuhiro Hiwada, Shinichi Asanuma
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Publication number: 20150312438Abstract: According to one embodiment, an image processing device includes a line memory that stores an input image by a plurality of rows; a defect correcting circuit that performs defect correction on the input image based on image data stored in the line memory; a binning circuit that generates a low pass image having a lower spatial frequency than the input image by binning the input image subjected to the defect correction; a frame buffer that stores the low pass image; a filter that generates a high pass image having a higher spatial frequency than the low pass image by filtering the input image subjected to the defect correction; and a mixing circuit that mixes the low pass image with the high pass image.Type: ApplicationFiled: July 2, 2015Publication date: October 29, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukiyasu TATSUZAWA, Kazuhiro HIWADA, Tatsuji ASHITANI
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Patent number: 9148595Abstract: According to one embodiment, a solid state imaging device includes a first image sensor, a second image sensor, and an imaging processing circuit. A plurality of photoelectric conversion units are arranged in each of the first image sensor and the second image sensor. All of the photoelectric conversion units are configured to include pixels with different charge storage times. The imaging processing circuit includes an output combining unit. The output combining unit combines outputs by the pixels with different charge storage times with respect to each of the photoelectric conversion units.Type: GrantFiled: September 14, 2012Date of Patent: September 29, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shiroshi Kanemitsu, Tatsuji Ashitani, Miho Iizuka
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Publication number: 20150237287Abstract: According to one embodiment, a solid-state imaging apparatus includes a pixel array, a first vertical signal line, a second vertical signal line, and a control unit. Each of cells includes a plurality of pixels. The first vertical signal line is connected to first cells. The second vertical signal line is connected to second cells. The control unit generates a timing signal. In each of the cells, two pixels are arrayed in a horizontal direction and at least two pixels are arrayed in a vertical direction. The control unit prioritizes ordering of pixels selected from the plurality of pixels to cause timings to read signals from the selected pixels to continue in the vertical direction. The control unit generates a timing signal that prioritizes ordering of the selected pixels over other pixels.Type: ApplicationFiled: July 23, 2014Publication date: August 20, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukiyasu TATSUZAWA, Tatsuji ASHITANI, Kazuhiro HIWADA
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Publication number: 20150201138Abstract: According to one embodiment, a solid-state imaging device comprises a pixel array wherein unit patterns are placed repeatedly the unit pattern along vertical and horizontal directions. The unit pattern has at least four pixels arranged vertically and two pixels arranged horizontally. The unit pattern is formed of pixels of a first group including two first green pixels and pixels of a second group including two second green pixels. The two first green pixels are arranged vertically with one of a red pixel and a blue pixel in between, and the two second green pixels are arranged vertically with one of a red pixel and a blue pixel in between.Type: ApplicationFiled: September 4, 2014Publication date: July 16, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiro HIWADA, Yukiyasu TATSUZAWA, Tatsuji ASHITANI
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Patent number: 9025065Abstract: According to one embodiment, a solid-state imaging device includes a high dynamic range (HDR) synthesizing unit. The HDR synthesizing unit synthesizes a first image signal from a first pixel and a second image signal from a second pixel. The first pixel is a pixel to which a first exposure time is applied. The second pixel is a pixel to which a second exposure time is applied. The second exposure time is shorter than the first exposure time. The first and second horizontal lines form a periodic array. The first horizontal line is a horizontal line formed by the first pixels. The second horizontal line is a horizontal line formed by the second pixels. In the periodic array, a combination of the first horizontal lines and the second horizontal lines of the number which is twice the number of first horizontal lines is formed as units.Type: GrantFiled: April 29, 2013Date of Patent: May 5, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yukiyasu Tatsuzawa, Kazuhiro Hiwada, Tatsuji Ashitani
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Patent number: 8976279Abstract: According to one embodiment, a light receiver includes a light reception module, a multi-exposure area selector, a multi-exposure controller, and a readout module. The light reception module includes N lines, each of the N lines having a plurality of light receiving elements. The multi-exposure area selector is configured to select one or a plurality of single-exposure lines and one or a plurality of multi-exposure lines. The multi-exposure controller is configured to, per the unit time, perform an exposure on the single-exposure lines one time for a first exposure time; and a first exposure and a second exposure on the multi-exposure lines. The readout module is configured to read exposure amounts of the lines line by line. The multi-exposure controller is configured to start the second exposure on the multi-exposure lines before reading of the exposure amounts of all the single-exposure lines is completed.Type: GrantFiled: February 8, 2013Date of Patent: March 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yukiyasu Tatsuzawa, Kazuhiro Hiwada, Tatsuji Ashitani, Jun Deguchi, Hideaki Majima, Motohiro Morisaki
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Publication number: 20150036033Abstract: According to one embodiment, in a pixel array unit, pixels configured to accumulate photoelectrically-converted charges are arranged in a matrix shape. A binning control unit performs control to lump together several pixels among the pixels between different lines of the pixel array unit. A frame-read control unit thins out and reads the lines to vary thinning positions of the lines lumped together by the binning control unit among two or more frames. A reconfiguration processing unit combines the two or more frames, in which the thinning positions are different, to thereby configure one frame.Type: ApplicationFiled: March 5, 2014Publication date: February 5, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yukiyasu TATSUZAWA, Kazuhiro HIWADA, Tatsuji ASHITANI
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Patent number: 8885075Abstract: According to embodiment, an image processing device includes a black level correcting section. The black level correcting section includes a first input restricting unit and a second input restricting unit. The second input restricting unit performs a second input restriction, having a second signal level range including a moving average as a reference, on a black level signal subjected to a first input restriction by the first input restricting unit. A correction amount calculation unit calculates a difference of an average of signal values subjected to the second input restriction and a black level standard value as a correction value to apply on an effective pixel signal.Type: GrantFiled: March 13, 2012Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shiroshi Kanemitsu, Tatsuji Ashitani, Yukiyasu Tatsuzawa
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Publication number: 20140263960Abstract: According to one embodiment, a solid-state imaging device includes a pixel array, a digital gain circuit, and a shading correction circuit. In the pixel array, pixels that accumulate photoelectrically converted charge are arranged in a matrix and the pixel array can control an exposure time of the pixels for each line. The digital gain circuit adjusts a digital gain of an output signal of the pixel array. The shading correction circuit corrects shading of the pixel array by controlling the exposure time of the pixels and the digital gain.Type: ApplicationFiled: November 22, 2013Publication date: September 18, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yukiyasu TATSUZAWA, Keizo Tashiro, Tatsuji Ashitani, Motohiro Morisaki
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Patent number: 8792025Abstract: According to embodiments, an image processing apparatus includes an image signal holding unit. The image processing apparatus uses an image signal passing through the common image signal holding unit to generate first, second and third correction values. The first correction value is a signal value applied to a pixel in which saturation of an output occurs in a saturation determination. The second correction value is a signal value subjected to a noise cancellation process. The third correction value is a signal value applied to a pixel in which defect occurs in a defect determination.Type: GrantFiled: March 13, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shiroshi Kanemitsu, Tatsuji Ashitani, Yukiyasu Tatsuzawa
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Publication number: 20140204253Abstract: According to one embodiment, a pixel array unit, an exposure period control unit, and a charge discharge control unit are provided. In the pixel array unit, pixels that accumulate photoelectrically converted charges are arranged in a matrix form. The exposure period control unit controls an exposure period of the pixels with respect to each of lines. The charge discharge control unit performs discharge control of charges accumulated in the pixels in a non-exposure period of the pixels with respect to each of lines.Type: ApplicationFiled: July 19, 2013Publication date: July 24, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Takahiko MIHARA, Yukiyasu Tatsuzawa, Tatsuji Ashitani, Yumi Yatsunami
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Publication number: 20140153841Abstract: According to one embodiment, an image processing device includes a line memory that stores an input image by a plurality of rows; a defect correcting circuit that performs defect correction on the input image based on image data stored in the line memory; a binning circuit that generates a low pass image having a lower spatial frequency than the input image by binning the input image subjected to the defect correction; a frame buffer that stores the low pass image; a filter that generates a high pass image having a higher spatial frequency than the low pass image by filtering the input image subjected to the defect correction; and a mixing circuit that mixes the low pass image with the high pass image.Type: ApplicationFiled: May 9, 2013Publication date: June 5, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yukiyasu TATSUZAWA, Kazuhiro HIWADA, Tatsuji ASHITANI
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Publication number: 20140111675Abstract: According to one embodiment, a solid-state imaging device includes a high dynamic range (HDR) synthesizing unit. The HDR synthesizing unit synthesizes a first image signal from a first pixel and a second image signal from a second pixel. The first pixel is a pixel to which a first exposure time is applied. The second pixel is a pixel to which a second exposure time is applied. The second exposure time is shorter than the first exposure time. The first and second horizontal lines form a periodic array. The first horizontal line is a horizontal line formed by the first pixels. The second horizontal line is a horizontal line formed by the second pixels. In the periodic array, a combination of the first horizontal lines and the second horizontal lines of the number which is twice the number of first horizontal lines is formed as units.Type: ApplicationFiled: April 29, 2013Publication date: April 24, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yukiyasu TATSUZAWA, Kazuhiro Hiwada, Tatsuji Ashitani
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Publication number: 20140085522Abstract: According to one embodiment, a solid-state imaging device includes a pixel array and a row selection circuit. The pixel array outputs a signal for each cell. The cell includes a plurality of pixels arranged in parallel in a column direction. The cells are arranged such that positions in the column direction of a first cell and a second cell are staggered. The first cell includes a blue pixel and a green pixel. The second cell includes a green pixel and a red pixel. In a binning process in the column direction, the row selection circuit selects rows including the green pixel in the first cell at the same time for the first cell. In the binning process in the column direction, the row selection circuit selects rows including the green pixel in the second cell at the same time for the second cell.Type: ApplicationFiled: February 1, 2013Publication date: March 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yumi YATSUNAMI, Tatsuji Ashitani, Yukiyasu Tatsuzawa, Takahiko Mihara
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Publication number: 20140063294Abstract: According to an embodiment, a high dynamic range synthesizing unit synthesizes first image signal and second image signal. A main control exposure value calculating unit calculates a main control exposure value based on a signal designated as a main control signal between the first image signal and the second image signal. A sub-control exposure value calculating unit multiplies the main control exposure value by a high dynamic range magnification and sets the multiplication result as a sub-control exposure value for a sub-control signal. The sub-control signal causes the main control signal to follow lightness adjustment.Type: ApplicationFiled: March 5, 2013Publication date: March 6, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yukiyasu Tatsuzawa, Kazuhiro Hiwada, Tatsuji Ashitani