Patents by Inventor Tatsumasa HIRATSUKA

Tatsumasa HIRATSUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240204030
    Abstract: An object is to provide a solid-state imaging device, a manufacturing method of a solid-state imaging device, and an electronic apparatus that are capable of reducing tensile stress produced between a covering film and a semiconductor element which is joined to a solid-state imaging element and which is covered with the covering film, and that allow transistors to be provided near chip ends. There is provided a configuration including a solid-state imaging element, a semiconductor element laminated on the solid-state imaging element and electrically connected to the solid-state imaging element, and a covering film that covers a non-lamination portion that is a region where the semiconductor element is not laminated, in a laminated surface of the solid-state imaging element where the semiconductor element is laminated, and further covers a peripheral side surface of the semiconductor element and forms a clearance between the peripheral side surface of the semiconductor element and the covering film.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 20, 2024
    Inventor: TATSUMASA HIRATSUKA
  • Publication number: 20230395636
    Abstract: To provide a solid-state imaging device capable of further improving quality and reliability of the solid-state imaging device. Provided is a solid-state imaging device including: a first substrate; a second substrate laminated on the first substrate by direct bonding on a side opposite to a light incident side of the first substrate, the second substrate having a size different from a size of the first substrate; a third substrate provided on a side opposite to a light incident side of the second substrate; and an insulating layer formed between the first substrate and the third substrate, in which the third substrate includes a well formed on a light incident side of the third substrate.
    Type: Application
    Filed: September 15, 2021
    Publication date: December 7, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kentaro AKIYAMA, Tatsumasa HIRATSUKA, Takahiro KAMEI, Yosuke NITTA