Abstract: In a sine-wave multiplier, signal components included in an output signal Qu1 and corresponding to the product of a third-order harmonic component of a first square wave W1 and an input signal Vi and the product of a fifth-order harmonic component of the first square wave W1 and the input signal Vi are offset by a signal component included in an output signal Qu2 and corresponding to the product of a fundamental component of a second square wave W2 and the input signal Vi and a signal component included in an output signal Qu3 and corresponding to the product of a fundamental component of a second square wave W3 and the input signal Vi.

Abstract: A capacitance detection device includes a first voltage output circuit configured to output a first alternating current voltage supplied to a shield electrode provided proximate to a detection electrode, a second voltage output circuit configured to output a second alternating current voltage whose frequency and phase are the same as that of the first alternating current voltage and whose amplitude is less than that of the first alternating current voltage, and a current output circuit configured to output a driving current Is to the detection electrode so that the difference between the voltage of the detection electrode and the second alternating current voltage becomes smaller, and output a detection signal corresponding to the driving current. The second voltage output circuit outputs a second alternating current voltage whose amplitude is adjusted so that the driving current in the absence of the object proximate to the detection electrode.

Abstract: Provided is a sine wave multiplication device of simple configuration, broad input signal level range, and minimal fluctuation in characteristics due to temperature. A signal component that corresponds to a product of an input signal Si and the third harmonic wave of a first square wave W1 included in an output signal Su1; and a signal component that corresponds to a product of the input signal Si and the fifth harmonic wave of the first square wave W1 is canceled by: a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W2 included in an output signal Su2; and a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W3 included in an output signal Su3.

Abstract: An input device includes at least one electrode including multiple detection terminals. The detection terminals are connected to an image data calculation unit. The image data calculation unit detects detection values that vary in accordance with an amount of electric charge detected through the detection terminals. Based on coefficient information values, the image data calculation unit calculates image data values each corresponding to capacitance of each of multiple sections. The coefficient information corresponds to different combinations of one of the multiple sections and one of the multiple detection terminals. The coefficient information represents a ratio of electric charge detected by the one of the detection terminals to an amount of electric charge charged in one of the sections.

Abstract: In a case where the amplitude of a detection voltage is increased, the amplitude of a drive current flowing in a detection-target capacitor also increases, and thus, the amplitude of a detection current also increases. In this case, the increase in amplitude of the detection current is not directly restricted by the condition of a power supply voltage range enabling a circuit to operate. For this reason, a current conversion ratio of a current output circuit or a capacitance value of a capacitor of a current-voltage conversion circuit is set to an appropriate value so as not to cause a voltage to exceed the power supply voltage range, thereby preventing the amplitude of the detection current from being restricted by the condition of the power supply voltage range. Therefore, it is possible to increase the amplitude of the detection voltage to a maximum within the power supply voltage range.

Abstract: In a sine-wave multiplier, signal components included in an output signal Qu1 and corresponding to the product of a third-order harmonic component of a first square wave W1 and an input signal Vi and the product of a fifth-order harmonic component of the first square wave W1 and the input signal Vi are offset by a signal component included in an output signal Qu2 and corresponding to the product of a fundamental component of a second square wave W2 and the input signal Vi and a signal component included in an output signal Qu3 and corresponding to the product of a fundamental component of a second square wave W3 and the input signal Vi.

Abstract: Provided is a sine wave multiplication device of simple configuration, broad input signal level range, and minimal fluctuation in characteristics due to temperature. A signal component that corresponds to a product of an input signal Si and the third harmonic wave of a first square wave W1 included in an output signal Su1; and a signal component that corresponds to a product of the input signal Si and the fifth harmonic wave of the first square wave W1 is canceled by: a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W2 included in an output signal Su2; and a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W3 included in an output signal Su3.

Abstract: In a case where the amplitude of a detection voltage is increased, the amplitude of a drive current flowing in a detection-target capacitor also increases, and thus, the amplitude of a detection current also increases. In this case, the increase in amplitude of the detection current is not directly restricted by the condition of a power supply voltage range enabling a circuit to operate. For this reason, a current conversion ratio of a current output circuit or a capacitance value of a capacitor of a current-voltage conversion circuit is set to an appropriate value so as not to cause a voltage to exceed the power supply voltage range, thereby preventing the amplitude of the detection current from being restricted by the condition of the power supply voltage range. Therefore, it is possible to increase the amplitude of the detection voltage to a maximum within the power supply voltage range.

Abstract: An electrostatic capacitance detection circuit includes a charge amplifier that has an operational amplifier in which a capacitor is provided on a feedback path, and into which a signal including detection of electric charge of an inter-electrode capacitor of a sensor electrode and electric charge due to an external noise, and a selection switch that can switch a direction of a capacitor that is connected to input and output terminals of the charge amplifier through a feedback path that switches the direction of the capacitor depending on a direction of electric charge flowing in from a detection-side electrode of the sensor electrode, due to a drive signal applied to the sensor electrode.

Abstract: A coordinate detecting device includes a plurality of first electrodes, a plurality of second electrodes, a capacitance detecting circuit, a first electrode switch, and a second electrode switch. All of the second electrodes are connected to a power supply by the second electrode switch and the first electrodes are selectively connected to the capacitance detecting circuit by the first electrode switch, thereby detecting a first coordinate. All of the first electrodes are connected to the power supply by the first electrode switch and the second electrodes are selectively connected to the capacitance detecting circuit by the second electrode switch, thereby detecting a second coordinate. When a plurality of first coordinates or a plurality of second coordinates are detected, capacitances between the first and second electrodes corresponding to combinations of the detected first and second coordinates are measured, thereby specifying the position of the detection target.

Abstract: An electrostatic capacitance detection circuit includes a charge amplifier that has an operational amplifier in which a capacitor is provided on a feedback path, and into which a signal including detection of electric charge of an inter-electrode capacitor of a sensor electrode and electric charge due to an external noise, and a selection switch that can switch a direction of a capacitor that is connected to input and output terminals of the charge amplifier through a feedback path that switches the direction of the capacitor depending on a direction of electric charge flowing in from a detection-side electrode of the sensor electrode, due to a drive signal applied to the sensor electrode.

Abstract: An image display method and apparatus for generating display data from predetermined high-order bits of original image data, the display data reflecting an error of low-order bits in the original image data. The display data is used to drive each of pixels arranged in line and column directions. The high-order three bits of six-bit original image data are regarded as intra-frame process data. A process value is determined based on the low-order three bits of the original image data, on a frame number, on a line number and on a column number. That process value is added to the least significant bit of the intra-frame process value made of the high-order three bits, whereby three-bit display data is generated. The addition of the process value evenly distributes the gray level error of the low-order three bits within each frame and between frames for simulated high quality gray level display.

Abstract: A coordinate detecting device includes a plurality of first electrodes, a plurality of second electrodes, a capacitance detecting circuit, a first electrode switch, and a second electrode switch. All of the second electrodes are connected to a power supply by the second electrode switch and the first electrodes are selectively connected to the capacitance detecting circuit by the first electrode switch, thereby detecting a first coordinate. All of the first electrodes are connected to the power supply by the first electrode switch and the second electrodes are selectively connected to the capacitance detecting circuit by the second electrode switch, thereby detecting a second coordinate. When a plurality of first coordinates or a plurality of second coordinates are detected, capacitances between the first and second electrodes corresponding to combinations of the detected first and second coordinates are measured, thereby specifying the position of the detection target.

Abstract: An image display method and apparatus for generating display data from predetermined high-order bits of original image data, the display data reflecting an error of low-order bits in the original image data. The display data is used to drive each of pixels arranged in line and column directions. The high-order three bits of six-bit original image data are regarded as intra-frame process data. A process value is determined based on the low-order three bits of the original image data, on a frame number, on a line number and on a column number. That process value is added to the least significant bit of the intra-frame process value made of the high-order three bits, whereby three-bit display data is generated. The addition of the process value evenly distributes the gray level error of the low-order three bits within each frame and between frames for simulated high quality gray level display.

Abstract: A capacitance detecting circuit detects the variations of capacitances at intersections of a plurality of column lines and a plurality of row lines opposite to the column lines and then converts the variations of capacitances into electrical signals. The capacitance detecting circuit includes a column line driving means that drives the column lines, a comparator that is connected to the row lines to convert charges stored in capacitors formed at the intersections of the driven column lines and the row lines into a measured voltage, and that compares the measured voltage with a predetermined set value to output charging or discharging signals, a constant current source that performs charging or discharging on the charges in response to the charging or discharging signals, and a capacitor that stores charges by means of the charging or discharging current. In the capacitance detecting circuit, a voltage between both ends of the capacitor is output as the electrical signal.

Abstract: A shift register having a plurality of stages connected in cascade shifts an output signal by a plurality of clocks having different phases. Each of the stage includes an input diode to which a signal is input from a preceding stage, a capacitor for holding charge having a voltage level of the input signal, a first transistor that is turned on or off by the held voltage level to output an output signal to a following stage in synchronization with a clock signal, and a second transistor connected between the input diode and an output terminal. A control electrode of the second transistor is connected to the input diode in the following stage. The second transistor has a clamping function for discharging the accumulated charge and turning off the first transistor when the clock signal is phase-shifted.

Abstract: A capacitance detecting circuit detects, in terms of voltage, change in capacitance at intersections of a plurality of column lines and a plurality of row lines crossing each other. The capacitance detecting circuit includes a column-line driving unit for driving a column line; a row-line selector for selecting a specific row line from the plurality of row lines; and a capacitance calculator for calculating a capacitance at an intersection of the specific row line and the driven column line based on a reference current that flows in relation to a reference capacitance and a current that flows in relation to the capacitance at the intersection.

Abstract: A capacitance detecting circuit detects the variations of capacitances at intersections of a plurality of column lines and a plurality of row lines opposite to the column lines and then converts the variations of capacitances into electrical signals. The capacitance detecting circuit includes a column line driving means that drives the column lines, a comparator that is connected to the row lines to convert charges stored in capacitors formed at the intersections of the driven column lines and the row lines into a measured voltage, and that compares the measured voltage with a predetermined set value to output charging or discharging signals, a constant current source that performs charging or discharging on the charges in response to the charging or discharging signals, and a capacitor that stores charges by means of the charging or discharging current. In the capacitance detecting circuit, a voltage between both ends of the capacitor is output as the electrical signal.

Abstract: A shift register having a plurality of stages connected in cascade shifts an output signal by a plurality of clocks having different phases. Each of the stage includes an input diode to which a signal is input from a preceding stage, a capacitor for holding charge having a voltage level of the input signal, a first transistor that is turned on or off by the held voltage level to output an output signal to a following stage in synchronization with a clock signal, and a second transistor connected between the input diode and an output terminal. A control electrode of the second transistor is connected to the input diode in the following stage. The second transistor has a clamping function for discharging the accumulated charge and turning off the first transistor when the clock signal is phase-shifted.

Abstract: The present invention provides a load capacity driving circuit capable of implementing low power consumption. Switches become closed in an initialization period, and a constant current source allows a bias current to flow through a drain of a MOS transistor, which causes a voltage determined by the current to be generated between a source and a gate thereof. A differential voltage between the potential of the gate of the MOS transistor and an input voltage is stored in a capacitor, and a load capacitor is connected to Vss to be discharged. In a subsequent output period, the switches become open, and switches become closed. Then, the capacitor is connected to the load capacitor, and the MOS transistor is turned on due to a decrease in the potential of the gate, so that the load capacitor is charged until the potential of the gate is restored.