Abstract: A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups.

Abstract: A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups.

Abstract: In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more efficiently. A processor includes a plurality of logic block circuits, which include at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits. The processor further includes, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.

Abstract: A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.

Abstract: In processors having a multicore, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block in a multicore processor such as a CMP comprising a plurality of processor cores makes it possible to perform LSI tests more efficiently.

Abstract: Each of a plurality of memory blocks returns data in different latency in reply to a data request from a request source. The closer a request destination memory block is to the request source, in the shorter latency the data is returned.

Abstract: A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.

Abstract: When a branch instruction for awaiting an event is detected in an information processing apparatus which performs a pipeline process including a branch prediction, a branch prediction for the branch instruction is suppressed. As a result, a prefetch operation for an instruction subsequent to the branch instruction is promoted, and the subsequent instruction is immediately executed when the event to be awaited occurs.

Abstract: A pipeline computer having functions of scoreboard control includes a dependency detection unit provided in the scoreboard for detecting dependency of data between a preceding instruction and a following instruction, the preceding instruction being an instruction which executes prior to the following instruction; and an ensuring unit for the dependency of data detected by the detection unit based on an interlock operation at pipeline processes when an interruption occurs. An interruption instruction waits for completion of an instruction which already starts to execute prior to the interruption instruction, and all register bits on the scoreboard indicating the in use state are reset to the not used state to ensure the dependency of data.

Abstract: In a computer system having a coprocessor dedicated to arithmetic operations, one of the coprocessor and CPU is equipped with an abnormality decision section and the other is equipped with a transmission section which transmits to the abnormality decision section signals by which the abnormality decision section is permitted to decide whether abnormality has occurred. In a first arrangement, upon detecting that an instruction transferred from the CPU is abnormal, the coprocessor turns off a flag indicating that it is active. In the CPU, its internal storage state indicates that the coprocessor is active and the flag is received which indicates that the coprocessor is inactive. Thereby, the CPU is permitted to decide that abnormality has occurred. In a second arrangement, upon detecting abnormality, the coprocessor turns off that flag indicating that it is active and turns on a flag indicating that the buffer is full.

Abstract: When a selector selects a first input terminal, a first loop circuit is formed including first and second input buffer circuits and an output buffer circuit. When the selector selects a second input terminal, a second loop circuit is formed including the first input buffer circuit and the output buffer circuit. When the selector selects a third input terminal, a third loop circuit is formed including the first input buffer circuit, a variable delay line (VDL), and the output buffer circuit. From the oscillating frequencies of loop circuits each formed as a ring oscillator, their respective signal delay times are obtained. By equalizing characteristics of first and second input buffer circuits, through a mutual operation using the signal delay times of respective loop circuits, a propagation delay time over a timing signal supply path including the first input buffer circuit and the VDL and stretching to a flip-flop is obtained precisely.

Abstract: A register read control method for use with an information processing apparatus for executing a plurality of instructions in parallel during pipeline processing. The apparatus includes a register file, a register designation selector, a cache register, a selector, an arithmetic circuit, a register cache pass and a comparator. When the comparator detects a coincidence between the data in the cache register for the current instruction and the operand in the next instruction, the comparator causes the selector to select the register cache pass as input thereto and to move the contents of the cache register back directly to the cache register via the register cache pass.

Abstract: There are provided a means for storing an instruction, a first control means for decoding and executing the instruction of said means for storing during a timing period which is used in said instruction, a means for computing an address data required for execution of said instruction, a first storage means having a plurality of registers for storing said computed address data, a means for selecting specific number resister in the first storage means, by controlling of the first control means during a timing period which is not used in said instruction, a second storage means for storing temporarily said address data in the specific number register selected by said means for selecting, a second control means for decoding the instruction before the first control means decoding and finding out the instruction to be branch instruction, and a means for outputting the address data from the second storage means as a target address data, when the register of the first storage means designated by said branch instructi

Abstract: The invention provides a data processing apparatus wherein, when a trouble of a built-in RAM is detected, stopping of the system by a comparison check of the outputs of multiple CPUs is prevented and the trouble of the built-in RAM can be removed. The data processing apparatus includes a built-in RAM error detection section for detecting that an error occurs in a built-in RAM of any of processing sections, and an inhibition section for inhibiting, when the built-in RAM error detection section detects that a built-in RAM error occurs in at least one of the processing sections, the result of comparison outputted from the comparison section originating from the occurrence of the built-in RAM error. The data processing apparatus can be applied to various computer systems wherein multiple processing sections (CPUs) perform same operation and processing is performed while the outputs of the processing sections are compared with each other to confirm that the processing sections are performing same operation.