Patents by Inventor Tatsumi Sumi
Tatsumi Sumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7890283Abstract: The present invention is applicable to various sensor outputs including pulse signals and reduces cost for detecting malfunction. The malfunction detection system detects a malfunction in a sensor, and the malfunction detection system includes a sensor including a first terminal, and which outputs a sensor output current that varies a voltage level of the first terminal, a current output unit which varies the voltage level of the first terminal by outputting a constant current for judging to the sensor via the first terminal, and a judging unit which judges that the sensor is malfunctioning when the current for judging causes the voltage level of the first terminal to be equal to or higher than a threshold in a period different from a first period where the sensor output current causes the voltage level of the first terminal to be equal to or higher than the threshold.Type: GrantFiled: November 21, 2008Date of Patent: February 15, 2011Assignee: Panasonic CorporationInventors: Eiichi Sadayuki, Tatsumi Sumi
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Patent number: 7850086Abstract: The present invention extends the reading range between a contactless type information medium (semiconductor integrated circuit) and a reader/writer, which exchanges data in contactless communications with the contactless type information medium, and enables a stable data exchange even if the power supply voltage is lowered when data is returned from the contactless type information medium to the reader/writer. Specifically, when data is returned from the contactless type information medium, the data to be returned is held in the logic circuit section 200 capable of operating at a lower voltage than the non-volatile memory circuit section 300, and the reset detection lower limit voltage to be used by the reset generating circuit 160 during the data-returning period is set to be lower than that during periods other than the data-returning period.Type: GrantFiled: April 12, 2005Date of Patent: December 14, 2010Assignee: Panasonic CorporationInventors: George Nakane, Tatsumi Sumi
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Publication number: 20090164162Abstract: The present invention is applicable to various sensor outputs including pulse signals and reduces cost for detecting malfunction. The malfunction detection system detects a malfunction in a sensor, and the malfunction detection system includes a sensor including a first terminal, and which outputs a sensor output current that varies a voltage level of the first terminal, a current output unit which varies the voltage level of the first terminal by outputting a constant current for judging to the sensor via the first terminal, and a judging unit which judges that the sensor is malfunctioning when the current for judging causes the voltage level of the first terminal to be equal to or higher than a threshold in a period different from a first period where the sensor output current causes the voltage level of the first terminal to be equal to or higher than the threshold.Type: ApplicationFiled: November 21, 2008Publication date: June 25, 2009Applicant: PANASONIC CORPORATIONInventors: Eiichi SADAYUKI, Tatsumi SUMI
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Publication number: 20070188297Abstract: The present invention extends the reading range between a contactless type information medium (semiconductor integrated circuit) and a reader/writer, which exchanges data in contactless communications with the contactless type information medium, and enables a stable data exchange even if the power supply voltage is lowered when data is returned from the contactless type information medium to the reader/writer. Specifically, when data is returned from the contactless type information medium, the data to be returned is held in the logic circuit section 200 capable of operating at a lower voltage than the non-volatile memory circuit section 300, and the reset detection lower limit voltage to be used by the reset generating circuit 160 during the data-returning period is set to be lower than that during periods other than the data-returning period.Type: ApplicationFiled: April 12, 2005Publication date: August 16, 2007Inventors: George Nakane, Tatsumi Sumi
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Patent number: 7138699Abstract: A semiconductor integrated circuit includes a supply voltage generator for rectifying a signal received by an antenna coil and generating a supply voltage set at a predetermined voltage by a regulator, and a demodulator. The demodulator includes a demodulation circuit for demodulating an input signal and outputting the demodulated input signal, a resistor whose one end is connected to one end of the antenna coil, a diode whose anode is connected to the other end of the resistor and whose cathode is connected to a node located to the input end of the demodulation circuit, a first capacitance connected between a node at which the resistor and the diode are connected to each other and a grounding conductor, and a second capacitance connected between a node at which the diode and the demodulation circuit are connected to each other and a grounding conductor.Type: GrantFiled: September 8, 2003Date of Patent: November 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: George Nakane, Tatsumi Sumi
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Patent number: 7011252Abstract: In an IC card applicable to a plurality of data transfer methods and including a plurality of OSs, when power sufficient for the operation is supplied to the IC card, an initial OS selecting section activates one of the plural OSs as an initial OS on the basis of identification information stored in a nonvolatile memory. A transfer method determining section determines a data transfer method on the basis of data received from a reader/writer. An OS applicability determining section determines whether or not the determined data transfer method accords with a data transfer method corresponding to the currently employed OS. When the data transfer methods do not accord with each other, an OS switching section switches the currently employed OS to another OS.Type: GrantFiled: April 12, 2004Date of Patent: March 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mitsuyoshi Ohya, Tatsumi Sumi
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Publication number: 20060022041Abstract: A semiconductor integrated circuit includes a supply voltage generator for rectifying a signal received by an antenna coil and generating a supply voltage set at a predetermined voltage by a regulator, and a demodulator. The demodulator includes a demodulation circuit for demodulating an input signal and outputting the demodulated input signal, a resistor whose one end is connected to one end of the antenna coil, a diode whose anode is connected to the other end of the resistor and whose cathode is connected to a node located to the input end of the demodulation circuit, a first capacitance connected between a node at which the resistor and the diode are connected to each other and a grounding conductor, and a second capacitance connected between a node at which the diode and the demodulation circuit are connected to each other and a grounding conductor.Type: ApplicationFiled: September 8, 2003Publication date: February 2, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: George Nakane, Tatsumi Sumi
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Patent number: 6907088Abstract: In a contactless IC card that performs envelope detection on an ASK-modulated carrier wave and demodulates the carrier wave to recover data piggybacked thereon, demodulation is suspended during periods where there is no possibility of a change of a data value (from data 0 to data 1, or from data 1 to data 0) in the digital data piggybacked on the carrier wave. In so doing, incorrect data recovery can be prevented even when noise arises in power supply voltage waveform due to power consumption of an internal memory or the like.Type: GrantFiled: September 19, 2000Date of Patent: June 14, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Joji Nakane, Tatsumi Sumi
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Patent number: 6882193Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.Type: GrantFiled: March 10, 2004Date of Patent: April 19, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshige Hirano, Kouji Asari, Tatsumi Sumi
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Patent number: 6848620Abstract: A semiconductor integrated circuit is provided to allow a stable operation even in a short distance where an IC card is in contact with a reader/writer. In a semiconductor integrated circuit for a noncontact IC card that obtains driving power supply by carrying superimposed data, obtained voltage does not become overvoltage and data can be demodulated with stability regardless of a change in communication distance. Inputs of a system (including a rectifier circuit and a power supply circuit) producing power supply from an antenna coil of the IC card which receives radio waves transmitted from a reader/writer, and of a demodulator circuit are connected via a path separated from the output of the rectifier circuit. Thus, a power supply voltage range can be set within a permissible value and a rate of change in input of the demodulator circuit can be obtained regardless whether the communication distance is short or long.Type: GrantFiled: April 10, 2002Date of Patent: February 1, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: George Nakane, Tatsumi Sumi
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Patent number: 6822493Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.Type: GrantFiled: February 20, 2003Date of Patent: November 23, 2004Assignee: Matsushita Electronics CorporationInventors: Hiroshige Hirano, Kouji Asari, Tatsumi Sumi
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Publication number: 20040200903Abstract: In an IC card applicable to a plurality of data transfer methods and including a plurality of OSs, when power sufficient for the operation is supplied to the IC card, an initial OS selecting section activates one of the plural OSs as an initial OS on the basis of identification information stored in a nonvolatile memory. A transfer method determining section determines a data transfer method on the basis of data received from a reader/writer. An OS applicability determining section determines whether or not the determined data transfer method accords with a data transfer method corresponding to the currently employed OS. When the data transfer methods do not accord with each other, an OS switching section switches the currently employed OS to another OS.Type: ApplicationFiled: April 12, 2004Publication date: October 14, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mitsuyoshi Ohya, Tatsumi Sumi
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Publication number: 20040169533Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.Type: ApplicationFiled: March 10, 2004Publication date: September 2, 2004Inventors: Hiroshige Hirano, Kouji Asari, Tatsumi Sumi
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Patent number: 6659352Abstract: A semiconductor integrated circuit which obtains a driving power from a carrier onto which data has been piggybacked, the semiconductor integrated circuit being characterized by demodulating data by correctly discriminating it even when the obtained power supply voltage has become overvoltage, and characterized by effectively using the power supplied by the carrier. The semiconductor integrated circuit includes: a two-voltage rectifier circuit as a power source circuit 111; a voltage regulator circuit 112 which exercises a control so that a power with a higher voltage (VDDH) used for demodulating data does not exceed a certain voltage value; a resistor 141; and a capacitor 142. With this construction, the voltage input to a regulator circuit 1121 as the reference voltage changes in correspondence to the change in voltage VDDH which is caused by the change in amplitude.Type: GrantFiled: May 31, 2000Date of Patent: December 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Asada, Joji Nakane, Tatsumi Sumi, Taketoshi Matsuura, Atsuo Inoue
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Publication number: 20030122597Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.Type: ApplicationFiled: February 20, 2003Publication date: July 3, 2003Inventors: Hiroshige Hirano, Kouji Asari, Tatsumi Sumi
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Patent number: 6538482Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.Type: GrantFiled: March 12, 2001Date of Patent: March 25, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshige Hirano, Kouji Asari, Tatsumi Sumi
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Publication number: 20020153997Abstract: A semiconductor integrated circuit is provided to allow a stable operation even in a short distance where an IC card is in contact with a reader/writer. In a semiconductor integrated circuit for a noncontact IC card that obtains driving power supply by carrying superimposed data, obtained voltage does not become overvoltage and data can be demodulated with stability regardless of a change in communication distance. Inputs of a system (including a rectifier circuit and a power supply circuit) producing power supply from an antenna coil of the IC card which receives radio waves transmitted from a reader/writer, and of a demodulator circuit are connected via a path separated from the output of the rectifier circuit. Thus, a power supply voltage range can be set within a permissible value and a rate of change in input of the demodulator circuit can be obtained regardless whether the communication distance is short or long.Type: ApplicationFiled: April 10, 2002Publication date: October 24, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: George Nakane, Tatsumi Sumi
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Publication number: 20010036119Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.Type: ApplicationFiled: March 12, 2001Publication date: November 1, 2001Inventors: Hiroshige Hirano, Kouji Asari, Tatsumi Sumi
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Patent number: 6246624Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.Type: GrantFiled: November 24, 1998Date of Patent: June 12, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshige Hirano, Kouji Asari, Tatsumi Sumi
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Patent number: 6067265Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.Type: GrantFiled: June 2, 1999Date of Patent: May 23, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Mukunoki, Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Tatsumi Sumi, Nobuyuki Moriwaki