Patents by Inventor Tatsumi Yamauchi

Tatsumi Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070182384
    Abstract: An inverter device is mounted on the rotating electric machine body The inverter device includes a module unit having a converter circuit and a control unit that controls the operation of the converter circuit. The converter circuit is configured by connecting a plurality of the following series circuits in parallel, each of the series circuits includes a P-channel MOS semiconductor device disposed at a higher potential side and an N-channel MOS semiconductor device disposed at a lower potential side which are electrically connected in series. An electric power that is supplied from a battery or an electric power that is supplied to the battery is controlled.
    Type: Application
    Filed: April 16, 2007
    Publication date: August 9, 2007
    Applicant: HITACHI LTD.
    Inventors: Shinji SHIRAKAWA, Mutsuhiro MORI, Masamitsu INABA, Tatsumi YAMAUCHI, Masahiro IWAMURA, Keiichi MASHINO, Masanori TSUCHIYA
  • Publication number: 20070139975
    Abstract: The inventive bi-directional DC-DC converter addresses a problem of an insufficient step-up ratio during the step-up operation that is caused when a turns ratio of the transformer is determined to, for example, match the step-up operation and also address a contrary problem of an insufficient step-down ratio during the step-down operation that is caused when a turns ratio is determined to match the step-up operation. In the inventive bi-directional DC-DC converter that uses a transformer for both step-down and step-up operations, a switching frequency for operating a switching device is set separately for the step-down and step-up operations. For example, when the switching frequency during the step-up operation is lower than the switching frequency during the step-down operation, the range in which the duty ratio in PWM control can be controlled is widened, compensating for step-up ratio insufficiency.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 21, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Tatsumi Yamauchi, Hiroyuki Shoji, Seigou Yukutake, Toshikazu Okubo
  • Patent number: 7208918
    Abstract: An inverter device is mounted on the rotating electric machine body The inverter device includes a module unit having a converter circuit and a control unit that controls the operation of the converter circuit. The converter circuit is configured by connecting a plurality of the following series circuits in parallel, each of the series circuits includes a P-channel MOS semiconductor device disposed at a higher potential side and an N-channel MOS semiconductor device disposed at a lower potential side which are electrically connected in series. An electric power that is supplied from a battery or an electric power that is supplied to the battery is controlled.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: April 24, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Mutsuhiro Mori, Masamitsu Inaba, Tatsumi Yamauchi, Masahiro Iwamura, Keiichi Mashino, Masanori Tsuchiya
  • Publication number: 20060192534
    Abstract: A generator having a field coil L, and an SW1 control circuit 2 for controlling field current flowing through the field coil L. When a generating operation of the generator is to be ended, a switch 1 SW1 is turned off to interrupt the field current flowing through the field coil L, and a switch 2 SW2 is turned off to allow the field current remaining the field coil L to the current path including a resistance element 1 with a resistance element capable of quickly attenuating the field current.
    Type: Application
    Filed: February 17, 2006
    Publication date: August 31, 2006
    Applicant: Hitachi, Ltd.
    Inventors: Tatsumi Yamauchi, Shinji Shirakawa, Masahiro Iwamura, Masamitsu Inaba, Keiichi Mashino, Keiji Kunii
  • Publication number: 20050237033
    Abstract: An inverter device is mounted on the rotating electric machine body The inverter device includes a module unit having a converter circuit and a control unit that controls the operation of the converter circuit. The converter circuit is configured by connecting a plurality of the following series circuits in parallel, each of the series circuits includes a P-channel MOS semiconductor device disposed at a higher potential side and an N-channel MOS semiconductor device disposed at a lower potential side which are electrically connected in series. An electric power that is supplied from a battery or an electric power that is supplied to the battery is controlled.
    Type: Application
    Filed: April 11, 2005
    Publication date: October 27, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Mutsuhiro Mori, Masamitsu Inaba, Tatsumi Yamauchi, Masahiro Iwamura, Keiichi Mashino, Masanori Tsuchiya
  • Publication number: 20050188706
    Abstract: An air conditioner and a power line communication system high in reliability and free of malfunction facilitates the installation work such as the wiring. The air conditioner for conducting communication through a power line includes a bridge unit connected to at least an outdoor unit through a transmission line, and at least an indoor unit connected from the power line through a blocking filter. A side of the bridge unit far from the outdoor unit is connected between the blocking filter and the indoor unit. The bridge unit subjects a signal from the outdoor unit to spread spectrum modulation and transmits it by superposing the resulting signal on the power line. The superposed signal is received and demodulated by the indoor unit.
    Type: Application
    Filed: January 13, 2005
    Publication date: September 1, 2005
    Inventors: Koichi Tokushige, Yasuyuki Kojima, Tatsumi Yamauchi, Makoto Ito, Noriyuki Bunko
  • Publication number: 20050005619
    Abstract: An air conditioning system is arranged to use a power line for communication. The air conditioning system includes one or more indoor units, one or more outdoor units, and a system controller for controlling the indoor units or outdoor units and executes communications between the indoor units and the outdoor units as overlapping a signal on the power line for supplying electric power. The outdoor units are connected with the system controller through a leased communication line. The indoor unit provides a power line communication device being connected with the power line. The outdoor unit provides a leased communication device being connected with the leased communication line. A bridge is also provided for connecting the leased communication line and the power line. The control information is exchanged mutually between the indoor units, the outdoor units and the system controller through the power line.
    Type: Application
    Filed: April 14, 2004
    Publication date: January 13, 2005
    Inventors: Yasuyuki Kojima, Noboru Akiyama, Takeshi Onaka, Tatsumi Yamauchi, Koichi Taniguchi, Koichi Tokushige, Noriyuki Bunkou, Keiji Sato
  • Patent number: 6798255
    Abstract: A semiconductor integrated circuit device including a driver circuit, a first long-distance wiring connected to the driver circuit, and a plurality of gate circuits connected over the entire length of the first long-distance wiring, so that an output signal of the driver circuit is received by the plurality of gate circuits via the first long-distance wiring, wherein a node arranged in the vicinity of an input terminal of the gate circuit connected to an input terminal of the driver circuit and an end of the first long-distance wiring is connected by a second long-distance wiring and a speed-increasing circuit.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: September 28, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Fumikazu Takahashi, Tatsumi Yamauchi, Fumio Murabayashi, Kazuhisa Miyamoto, Kazuharu Kuchimachi
  • Patent number: 6713975
    Abstract: A lighting apparatus capable of improving amenity and energy-saving and controlling a lighting load as a user intends to do. The lighting apparatus is connected to a network and controlling the lighting load corresponding to information from the network, and the lighting apparatus further comprises an automatic mode for controlling the lighting load corresponding to the information from the network, a manual mode for controlling the lighting load independently of the information from the network, and a switching means for switching between the automatic mode and the manual mode.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tatsumi Yamauchi, Fumio Murabayashi, Haruki Komatsu, Akio Inada
  • Patent number: 6657459
    Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: December 2, 2003
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Patent number: 6590425
    Abstract: There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: July 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, Hiromichi Yamada
  • Patent number: 6538866
    Abstract: A circuit for protecting a load from an overvoltage can be integrated together with the load on the same chip by an MOS transistor manufacture process. This overvoltage protecting circuit is composed of a surge protection circuit, an overvoltage detecting circuit and a switching circuit. The surge protection circuit including two MOS transistors operates so that a surge voltage applied to a power supply receiving terminal is clamped by virtue of the source-drain breakdown voltage of the two MOS transistors, thereby absorbing the surge energy. The overvoltage detecting circuit including two MOS transistors operates so that a DC voltage supplied from the surge protection circuit is monitored with the source-drain voltage of the two MOS transistors taken as a reference voltage, thereby detecting an overvoltage. An overvoltage detection output brings an MOS transistor of the switching circuit into a turned-off condition to protect the load.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: March 25, 2003
    Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.
    Inventors: Keiji Hanzawa, Masahiro Matsumoto, Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Kohei Sakurai, Atsushi Miyazaki
  • Patent number: 6539322
    Abstract: A sensor device is provided which included a digital arithmetic processing unit which performs arithmetic processing through a program stored therein in advance, a pulse generator for generating pulses through the program, and a unit for causing the output voltage of the sensor device to stay at either a power source voltage concerned or the ground voltage, when the pulses from the pulse generator are interrupted, thereby, a sensor device using digital arithmetic processing and outputting analogue voltages is provided allowing the host system to judge easily whether the sensor device is operating normally or is failing.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: March 25, 2003
    Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.
    Inventors: Masahiro Matsumoto, Kohei Sakurai, Fumio Murabayashi, Hiromichi Yamada, Tatsumi Yamauchi, Atsushi Miyazaki, Keiji Hanzawa
  • Patent number: 6489906
    Abstract: A &Dgr;&Sgr; type AD converter includes a local D/A converter having a SC integrator which is constructed by an analog switch operated at the first and second timings of an input 1, an analog switch operated at the first and second timings of an input 2, an analog switch operated at the first and second timings without selection of the input, a capacitor charged and discharged by these analog switches and an operational amplifier (21), a comparator (22), a D-type flip-flop (28), a switch (29) and reference voltage sources (30, 31).
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: December 3, 2002
    Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.
    Inventors: Masahiro Matsumoto, Fumio Murabayashi, Tatsumi Yamauchi, Keiji Hanzawa
  • Publication number: 20020175718
    Abstract: A semiconductor integrated circuit device including a driver circuit, a first long-distance wiring connected to the driver circuit, and a plurality of gate circuits connected over the entire length of the first long-distance wiring, so that an output signal of the driver circuit is received by the plurality of gate circuits via the first long-distance wiring, wherein a node arranged in the vicinity of an input terminal of the gate circuit connected to an input terminal of the driver circuit and an end of the first long-distance wiring is connected by a second long-distance wiring and a speed-increasing circuit.
    Type: Application
    Filed: August 17, 2001
    Publication date: November 28, 2002
    Inventors: Fumikazu Takahashi, Tatsumi Yamauchi, Fumio Murabayashi, Kazuhisa Miyamoto, Kazuharu Kuchimachi
  • Patent number: 6472917
    Abstract: A third gate circuit which is controlled by a clock signal and operates upon the detection of change of a signal on a critical path driven by a first gate circuit and transmits a signal provided by the first gate circuit to a second gate circuit is connected to the critical path at a position near the second gate circuit. The third gate circuits operates upon the detection of change of the signal to increase the speed of change of the signal. Thus, the ratio of a delay time attributable to wiring resistance in the critical path of a semiconductor integrated circuit is reduced, the speed of the critical path is increased and the operating frequency of the semiconductor integrated circuit can be improved.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: October 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Tatsumi Yamauchi, Kazuharu Kuchimachi
  • Patent number: 6467004
    Abstract: A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Shigeya Tanaka, Takashi Hotta, Tatsumi Yamauchi, Kazutaka Mori
  • Patent number: 6462580
    Abstract: The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: October 8, 2002
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Publication number: 20020130683
    Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.
    Type: Application
    Filed: May 14, 2002
    Publication date: September 19, 2002
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Publication number: 20020050799
    Abstract: A lighting apparatus capable of improving amenity and energy-saving and controlling a lighting load as a user intends to do. The lighting apparatus is connected to a network and controlling the lighting load corresponding to information from the network, and the lighting apparatus further comprises an automatic mode for controlling the lighting load corresponding to the information from the network, a manual mode for controlling the lighting load independently of the information from the network, and a switching means for switching between the automatic mode and the manual mode.
    Type: Application
    Filed: July 27, 2001
    Publication date: May 2, 2002
    Inventors: Tatsumi Yamauchi, Fumio Murabayashi, Haruki Komatsu, Akio Inada