Patents by Inventor Tatsunori Inoue
Tatsunori Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210257016Abstract: In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit.Type: ApplicationFiled: May 31, 2019Publication date: August 19, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hajime KIMURA, Yoshiyuki KUROKAWA, Tatsunori INOUE
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Publication number: 20210225310Abstract: A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.Type: ApplicationFiled: April 7, 2021Publication date: July 22, 2021Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Tatsunori INOUE
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Patent number: 11062666Abstract: A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.Type: GrantFiled: February 20, 2020Date of Patent: July 13, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Tatsunori Inoue
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Publication number: 20210174857Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.Type: ApplicationFiled: April 22, 2019Publication date: June 10, 2021Inventors: Shunpei YAMAZAKI, Kiyoshi KATO, Hajime KIMURA, Atsushi MIYAGUCHI, Tatsunori INOUE
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Publication number: 20210151463Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.Type: ApplicationFiled: December 29, 2020Publication date: May 20, 2021Inventors: Hajime KIMURA, Tatsunori INOUE
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Publication number: 20210134801Abstract: An electronic device including a semiconductor device capable of intermittent driving is provided. The electronic device includes a semiconductor device, and the semiconductor device includes a current mirror circuit, a bias circuit, and first to third transistors. The current mirror circuit includes a first output terminal and a second output terminal, and the current mirror circuit is electrically connected to a power supply line through the first transistor. The current mirror circuit has a function of outputting current corresponding to a potential of the first output terminal from the first output terminal and the second output terminal. The bias circuit includes a current source circuit and a current sink circuit, the current source circuit is electrically connected to the second output terminal through the second transistor, and the current sink circuit is electrically connected to the second output terminal through the third transistor.Type: ApplicationFiled: August 27, 2018Publication date: May 6, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shintaro HARADA, Tatsunori INOUE, Yoshiyuki KUROKAWA, Shunpei YAMAZAKI
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Patent number: 10886292Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.Type: GrantFiled: May 13, 2020Date of Patent: January 5, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hajime Kimura, Tatsunori Inoue
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Publication number: 20200382730Abstract: An imaging device with reduced power consumption is provided. The imaging device includes an imaging portion and an encoder. First image data obtained by the imaging portion is transmitted to the encoder. The encoder includes a first circuit that forms a neural network, and the first circuit conducts feature extraction by the neural network on a first image to generate second image data. Note that since the first circuit has a function of performing convolution processing using a weight filter, the encoder can perform computation with a convolutional neural network.Type: ApplicationFiled: April 20, 2018Publication date: December 3, 2020Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki KUROKAWA, Tatsunori INOUE
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Publication number: 20200279860Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.Type: ApplicationFiled: May 13, 2020Publication date: September 3, 2020Inventors: Hajime KIMURA, Tatsunori INOUE
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Publication number: 20200193927Abstract: A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.Type: ApplicationFiled: February 20, 2020Publication date: June 18, 2020Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Tatsunori INOUE
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Patent number: 10665604Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.Type: GrantFiled: July 16, 2018Date of Patent: May 26, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hajime Kimura, Tatsunori Inoue
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Patent number: 10650766Abstract: A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.Type: GrantFiled: January 22, 2018Date of Patent: May 12, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Tatsunori Inoue
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Patent number: 10411013Abstract: To provide a semiconductor device with large storage capacity and low power consumption. The semiconductor device includes an oxide semiconductor, a first transistor, a second transistor, and a dummy word line. A channel formation region in the first transistor and a channel formation region in the second transistor are formed in different regions in the oxide semiconductor. The dummy word line is provided to extend between the channel formation region in the first transistor and the channel formation region in the second transistor. By applying a predetermined potential to the dummy word line, the first transistor and the second transistor are electrically isolated in a region of the oxide semiconductor which intersects the dummy word line.Type: GrantFiled: January 17, 2017Date of Patent: September 10, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiromichi Godo, Tatsunori Inoue
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Patent number: 10290253Abstract: An object is to provide a semiconductor device that automatically adjusts the luminance of a display device. The semiconductor device includes an illuminometer, a threshold detector, a timing controller, a digital-to-analog converter circuit, a first display panel, and a second display panel. The illuminance of external light is measured with the illuminometer, and the threshold value of digital video data is determined by the threshold detector in accordance with the illuminance. The timing controller generates a signal for the first display panel or a signal for the second display panel on the basis of the threshold value and video data transmitted from the outside. The signal for the first display panel and the signal for the second display panel are input to one digital-to-analog converter circuit and converted into digital signals, and the obtained digital signals are input to a corresponding one of the first display panel and the second display panel.Type: GrantFiled: June 7, 2017Date of Patent: May 14, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsunori Inoue, Takeshi Aoki
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Publication number: 20190027493Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.Type: ApplicationFiled: July 16, 2018Publication date: January 24, 2019Inventors: Hajime KIMURA, Tatsunori INOUE
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Publication number: 20180211620Abstract: A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.Type: ApplicationFiled: January 22, 2018Publication date: July 26, 2018Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Tatsunori INOUE
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Publication number: 20170358254Abstract: An object is to provide a semiconductor device that automatically adjusts the luminance of a display device. The semiconductor device includes an illuminometer, a threshold detector, a timing controller, a digital-to-analog converter circuit, a first display panel, and a second display panel. The illuminance of external light is measured with the illuminometer, and the threshold value of digital video data is determined by the threshold detector in accordance with the illuminance. The timing controller generates a signal for the first display panel or a signal for the second display panel on the basis of the threshold value and video data transmitted from the outside. The signal for the first display panel and the signal for the second display panel are input to one digital-to-analog converter circuit and converted into digital signals, and the obtained digital signals are input to a corresponding one of the first display panel and the second display panel.Type: ApplicationFiled: June 7, 2017Publication date: December 14, 2017Inventors: Tatsunori INOUE, Takeshi AOKI
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Publication number: 20170213833Abstract: To provide a semiconductor device with large storage capacity and low power consumption. The semiconductor device includes an oxide semiconductor, a first transistor, a second transistor, and a dummy word line. A channel formation region in the first transistor and a channel formation region in the second transistor are formed in different regions in the oxide semiconductor. The dummy word line is provided to extend between the channel formation region in the first transistor and the channel formation region in the second transistor. By applying a predetermined potential to the dummy word line, the first transistor and the second transistor are electrically isolated in a region of the oxide semiconductor which intersects the dummy word line.Type: ApplicationFiled: January 17, 2017Publication date: July 27, 2017Inventors: Hiromichi GODO, Tatsunori INOUE
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Patent number: 9000442Abstract: To simply provide a flexible light-emitting device with long lifetime. To provide a flexible light-emitting device with favorable display characteristics, high yield, and high reliability without display unevenness.Type: GrantFiled: January 13, 2011Date of Patent: April 7, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaoru Hatano, Takaaki Nagata, Nozomu Sugisawa, Tatsuya Okano, Akihiro Chida, Tatsunori Inoue
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Publication number: 20110175101Abstract: To simply provide a flexible light-emitting device with long lifetime. To provide a flexible light-emitting device with favorable display characteristics, high yield, and high reliability without display unevenness.Type: ApplicationFiled: January 13, 2011Publication date: July 21, 2011Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaoru HATANO, Takaaki NAGATA, Nozomu SUGISAWA, Tatsuya OKANO, Akihiro CHIDA, Tatsunori INOUE