Abstract: The invention provides a semiconductor integrated circuit device that includes a combination circuit incorporated in a chip, plural input pads and output pads, and a shift register made up with plural SFFs in which the input pins and output pins of the consecutive SFFs are connected, respectively, to the input pads and the output pads directly or via the combination circuit. In this configuration, the output pads and the input pads are connected to each other inside the chip to thereby form a test path.

Abstract: In a test circuit for a semiconductor integrated circuit, a counter circuit generates a control signal based on a comparison result between test results and expected data from a comparison circuit and outputs the control signal to a tri state buffer. The tri state buffer operates based on the received control signal. The counter circuit outputs the generated control signal to the tri state buffer in order that the tri state buffer outputs the test result to the outside of the test circuit only when the test results are not equal to the expected data.

Abstract: The invention provides a semiconductor integrated circuit device that includes a combination circuit incorporated in a chip, plural input pads and output pads, and a shift register made up with plural SFFs in which the input pins and output pins of the consecutive SFFs are connected, respectively, to the input pads and the output pads directly or via the combination circuit. In this configuration, the output pads and the input pads are connected to each other inside the chip to thereby form a test path.

Abstract: A semiconductor integrated circuit built therein scan paths comprising scan paths, connected to a combinational circuit block, each consisting of a plurality of SFFs, and a bidirectional pin, via which test patterns are not only input to the scan paths to apply the test patterns to the combinational circuit block when a control signal is set to an input mode but also output the results from the combinational circuit block. Control of the direction of a signal input to or output from the bidirectional pin is controlled by inputting the control signal from an external pin, or by adopting an internal circuit consisting of counters.

Abstract: In a semiconductor integrated circuit device, a pattern generator 12 generates burn-in test patterns based on control signals received through external terminals 11 and corresponding I/O buffers, and provides the generated burn-in test patterns to input terminals 5 of a DRAM 2. The burn-in test operation is performed only by using the control signals received through the external terminals 11 and the corresponding I/O buffers. The burn-in test operation is performed by a small number of access operations to the I/O buffers because the number of the access operations to the I/O buffers may be decreased when comparing with a conventional one. Thereby, the accuracy of the reliability test for the DRAM 2 may be increased.

Abstract: A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capacity for storing defective bits to make the testing apparatus inexpensive, and that easily cope with increase and decrease in IO numbers. A large number of IO outputs MOUT are collectively compared with a specified expected value, and as a result resultant judgment information DOUT is outputted to an error information acquiring device 22, and an analyzing device 23 reads table information sequentially from each block to obtain replacing data, and the replacing data are outputted serially to the external tester through the external I/F circuit 24. The redundant memory cell 4a itself can be made to compare with a specified expected value in the same manner as other memory cells 4 or the like.

Abstract: A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capacity for storing defective bits to make the testing apparatus inexpensive, and that easily cope with increase and decrease in IO numbers. A large number of IO outputs MOUT are collectively compared with a specified expected value, and as a result resultant judgment information DOUT is outputted to an error information acquiring device 22, and an analyzing device 23 reads table information sequentially from each block to obtain replacing data, and the replacing data are outputted serially to the external tester through the external I/F circuit 24. The redundant memory cell 4a itself can be made to compare with a specified expected value in the same manner as other memory cells 4 or the like.

Abstract: An integrated circuit including a plurality of functional blocks sharing synchronizing control transistors for carrying out synchronizing control of the plurality of functional blocks in common in response to a clock signal supplied to their control terminals. This makes it possible to reduce the number of the synchronizing control transistors as compared with a conventional circuit in which each of the functional blocks includes synchronizing control transistors independently.

Abstract: A semiconductor integrated circuit device having a CPU or a logic circuit 4, a DRAM 2, and a plurality of selectors 8 mounted on a semiconductor chip. The selectors 8 are formed on a wiring 5 including a plurality of lines through which the CPU or the logic circuit 4 is connected to the DRAM 2. According to a control signal received through a wiring 6, a wiring 7 for transferring test patterns is connected to the DRAM 2, or the CPU or the logic circuit 4 is connected to the DRAM 2.

Abstract: Power consumption is reduced in a semiconductor integrated circuit. In a conventional flip-flop circuit, there is a transistor between one side current electrode of a PMOS transistor (PTr7) and an node (V0) of a power source. This transistor is deleted and one side current electrode of (PTr7) is connected to an node (D2). In a similar manner, one side current electrode of (PTr13) is connected to an node (D13), one side current electrode of an NMOS transistor (NTr6) is connected to an node (D6), and one side current electrode of (NTr14) is connected to an node (D12). Thus, by deleting transistors, the capacity of transistors which are to be driven by a clock signal is reduced, and therefore, power consumption is reduced.

Abstract: A logical synthesizing device and logical synthesizing method capable of generating a net list from a feedback loop added flip-flop excellent in layout efficiency. In a cell library, cells of feedback loop added flip-flop are newly registered together with existing various cells. The feedback loop portion of this feedback loop added flip-flop is formed in an optimum layout composition in consideration of the setup time and hold time. A logical synthesizing section, using the cells registered in the cell library, generates a net list for realizing a logical function description, and outputs to a test design section At this time, the feedback loop forming portion in the input and output of the flip-flop generates the net list by using the feedback loop added flip-flop.

Abstract: Programmable logical blocks (3a to 3c) selected from a block library including information of a plurality of types of programmable logical blocks are disposed in a core region of a semiconductor integrated circuit (100). The degree of freedom of designing a field programmable gate array (FPGA) and the degree of integration are increased. A logic LSI is permitted to have redundancy to flexibly cope with design changes. This affords reduction in develop period and develop costs.

Abstract: A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an arithmetic circuit register circuits and a logic circuit form a bit slice cell and an arithmetic circuit register circuits and a logic circuit form a bit slice cell. The bit slice cells are arranged generally in parallel to form a bit slice circuit which prevents redundant lines for connecting the functional circuits, whereby the bit slice circuit is developed in a short period without a decreased degree of integration and prolonged delay time.

Abstract: In designing a layout of a semiconductor integrated circuit device having a large scale circuit block and logic circuit elements provided together, a power supply connecting line is formed rectilinearly to increase the integration density, reduce power supply noise and achieve automation of layout and interconnection. The semiconductor integrated circuit device includes one large scale circuit block and a plurality of logic circuit elements. VDD and GND annular power supply interconnecting lines are provided to surround the large scale circuit block. The annular power supply interconnecting lines extending in the lateral direction are divided into two lines to be disposed, respectively. Connection of the logic circuit elements and the annular power supply interconnecting lines are made by rectilinear VDD and GND power supply branch interconnecting lines.