Patents by Inventor Tatsunori Usugi
Tatsunori Usugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9722590Abstract: A skew adjustment circuit includes: flip flop circuits for taking in an input signal in response to first clock signals; a clock phase adjustment circuit for adjusting phases of second clock signals, based on the second clock signals generated based on a reference clock signal and an output signal from the flip flop circuits; a phase interval detection circuit for detecting a phase interval between the first clock signals, based on a reference value; and a phase interval adjustment circuit for performing adjustment such that phase intervals become equal to each other between the second clock signals adjusted by the clock phase adjustment circuit, based on a skew adjustment signal from the phase interval detection circuit. The reference value is obtained by calibration, and the second clock signals adjusted by the phase interval adjustment circuit are provided as the first clock signals to the flip flop circuits.Type: GrantFiled: June 13, 2016Date of Patent: August 1, 2017Assignee: Hitachi, Ltd.Inventors: Tatsunori Usugi, Kouzaburou Kurita, Takemasa Komori, Junya Nasu
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Publication number: 20170214398Abstract: A skew adjustment circuit includes: flip flop circuits for taking in an input signal in response to first clock signals; a clock phase adjustment circuit for adjusting phases of second clock signals, based on the second clock signals generated based on a reference clock signal and an output signal from the flip flop circuits; a phase interval detection circuit for detecting a phase interval between the first clock signals, based on a reference value; and a phase interval adjustment circuit for performing adjustment such that phase intervals become equal to each other between the second clock signals adjusted by the clock phase adjustment circuit, based on a skew adjustment signal from the phase interval detection circuit. The reference value obtained by calibration, and the second clock signals adjusted by the phase interval adjustment circuit are provided as the first clock signals to the flip flop circuits.Type: ApplicationFiled: June 13, 2016Publication date: July 27, 2017Inventors: Tatsunori USUGI, Kouzaburou KURITA, Takemasa KOMORI, Junya NASU
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Patent number: 8625730Abstract: In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a reference clock. Then, outputs of the first and second phase comparators are weighted by a result of the phase comparison of a receive signal and the feedback clock, and phase adjustment of the feedback clock is phase adjusted using the weighted outputs. Thereby, it is possible to lower a frequency of the reference clock and consequently to suppress power consumption.Type: GrantFiled: July 12, 2011Date of Patent: January 7, 2014Assignee: Hitachi, Ltd.Inventors: Tatsunori Usugi, Daisuke Hamano
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Patent number: 8547148Abstract: A digital compensation phase locked loop circuit of a semiconductor device includes a phase locked loop circuit including a voltage controlled oscillator having capacitors at oscillation nodes and consecutively controlled by an applied voltage, and a digital compensation circuit which variably controls the capacitors at the oscillation nodes of the voltage controlled oscillator in accordance with an input phase difference. A gain of the conventional voltage controlled oscillator whose gain is determined by an applied voltage is discretely changed by a control signal of the digital compensation circuit. The digital compensation circuit dynamically controls the gain so as to secure the optimum phase margin by applying a load (capacitor) to the oscillation node of the voltage controlled oscillator with respect to a phase lead and decreasing the load (capacitor) with respect to a phase delay.Type: GrantFiled: February 12, 2011Date of Patent: October 1, 2013Assignee: Hitachi, Ltd.Inventors: Akira Matsumoto, Tatsunori Usugi
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Patent number: 8456205Abstract: Disclosed is a phase-frequency comparator stabilizing a loop band width by a simple circuit, there is provided a phase-frequency comparator which is a phase-frequency comparator of inputting a reference clock and a feedback clock and outputting an up signal to a frequency synthesizer and a down signal to the frequency synthesizer, which is provided with a first phase-frequency comparing circuit, a second phase comparing circuit, and a delay circuit portion inputting the reference clock and the feedback clock and providing a predetermined relative delay to an input of the first phase-frequency comparing circuit and an input of the second phase comparing circuit, in which frequency comparison is carried out by the first phase-frequency comparing circuit, and phase comparison is carried out by the first phase-frequency comparing circuit and the second phase comparing circuit controlling a latch.Type: GrantFiled: January 8, 2011Date of Patent: June 4, 2013Assignee: Hitachi, Ltd.Inventors: Tatsunori Usugi, Takeshi Isezaki, Takeshi Koyama
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Publication number: 20120188013Abstract: In a receiving circuit, and in a semiconductor device and an information processing system including the receiving circuit, the receiving circuit is configured to amplify a high-speed signal by a greater gain than a low-speed signal with a low electric power consumption. The receiving circuit includes a first amplifier and a second amplifier having a cutoff frequency lower than a cutoff frequency of the first amplifier. A received signal is inputted to the first amplifier and the second amplifier, an output from the second amplifier is subtracted from an output from the first amplifier, and a result is outputted from the receiving circuit.Type: ApplicationFiled: January 12, 2012Publication date: July 26, 2012Inventors: Yuji USHIO, Daisuke Hamano, Tatsunori Usugi
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Publication number: 20120187986Abstract: A receiving circuit that consumes less electric power is provided. The present invention provides a latch circuit that latches a differential signal by interrupting an electric current generated by a differential input using a corresponding differential output when the differential signal is differentially amplified. By using the latch circuit, transmitted data can be received even if the voltage difference of the differential signal components of the received signal is small. As a result, the number of amplifiers can be reduced, thereby enabling the power consumption of the receiver to be reduced.Type: ApplicationFiled: January 12, 2012Publication date: July 26, 2012Inventors: Daisuke Hamano, Tatsunori Usugi
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Publication number: 20120051480Abstract: In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a reference clock. Then, outputs of the first and second phase comparators are weighted by a result of the phase comparison of a receive signal and the feedback clock, and phase adjustment of the feedback clock is phase adjusted using the weighted outputs. Thereby, it is possible to lower a frequency of the reference clock and consequently to suppress power consumption.Type: ApplicationFiled: July 12, 2011Publication date: March 1, 2012Inventors: Tatsunori USUGI, Daisuke Hamano
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Publication number: 20110234274Abstract: A digital compensation phase locked loop circuit of a semiconductor device includes a phase locked loop circuit including a voltage controlled oscillator having capacitors at oscillation nodes and consecutively controlled by an applied voltage, and a digital compensation circuit which variably controls the capacitors at the oscillation nodes of the voltage controlled oscillator in accordance with an input phase difference. A gain of the conventional voltage controlled oscillator whose gain is determined by an applied voltage is discretely changed by a control signal of the digital compensation circuit. The digital compensation circuit dynamically controls the gain so as to secure the optimum phase margin by applying a load (capacitor) to the oscillation node of the voltage controlled oscillator with respect to a phase lead and decreasing the load (capacitor) with respect to a phase delay.Type: ApplicationFiled: February 12, 2011Publication date: September 29, 2011Inventors: Akira MATSUMOTO, Tatsunori Usugi
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Publication number: 20110175648Abstract: Disclosed is a phase-frequency comparator stabilizing a loop band width by a simple circuit, there is provided a phase-frequency comparator which is a phase-frequency comparator of inputting a reference clock and a feedback clock and outputting an up signal to a frequency synthesizer and a down signal to the frequency synthesizer, which is provided with a first phase-frequency comparing circuit, a second phase comparing circuit, and a delay circuit portion inputting the reference clock and the feedback clock and providing a predetermined relative delay to an input of the first phase-frequency comparing circuit and an input of the second phase comparing circuit, in which frequency comparison is carried out by the first phase-frequency comparing circuit, and phase comparison is carried out by the first phase-frequency comparing circuit and the second phase comparing circuit controlling a latch.Type: ApplicationFiled: January 8, 2011Publication date: July 21, 2011Inventors: Tatsunori USUGI, Takeshi Isezaki, Takeshi Koyama
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Patent number: 7369069Abstract: A semiconductor device including a clock signal generation circuit and a plurality of circuit blocks operating in synchronization with the clock signal, in which each of the plurality of the circuit blocks conducts resetting treatment receiving the interruption signal reset_in outputted in synchronization with the clock signal in the course of frequency acquisition, whereby the timing margin is improved greatly to facilitate the design of timing for a case of conducting interruption between a plurality of circuit blocks operating at high speed simultaneously and decrease circuit scale and power consumption.Type: GrantFiled: July 7, 2006Date of Patent: May 6, 2008Assignee: Hitachi, Ltd.Inventors: Tatsunori Usugi, Kazuhisa Suzuki, Masatoshi Tsuge
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Publication number: 20070040715Abstract: A semiconductor device including a clock signal generation circuit and a plurality of circuit blocks operating in synchronization with the clock signal, in which each of the plurality of the circuit blocks conducts resetting treatment receiving the interruption signal reset_in outputted in synchronization with the clock signal in the course of frequency acquisition, whereby the timing margin is improved greatly to facilitate the design of timing for a case of conducting interruption between a plurality of circuit blocks operating at high speed simultaneously and decrease circuit scale and power consumption.Type: ApplicationFiled: July 7, 2006Publication date: February 22, 2007Inventors: Tatsunori Usugi, Kazuhisa Suzuki, Masatoshi Tsuge