Abstract: A method for designing a manufacturing process of an electronic device includes calibrating a technology computer-aided design system by fitting simulation parameters of manufacturing process and electrical characteristic simulations, using first feature of commercial manufacturing process of first electronic device manufactured by first manufacturing facilities, and first electrical characteristic of the first electronic device; acquiring second feature of trial manufacturing process of second electronic device manufactured by second manufacturing facilities, and second electrical characteristic of the second electronic device; calculating simulation electrical characteristic of the second electronic device by substituting the second feature to the manufacturing process simulation corresponding to the trial manufacturing process; comparing the second electrical characteristic with the simulation electrical characteristic; and creating design specification of commercial manufacturing process of the second man

Abstract: A method for designing a manufacturing process of an electronic device includes calibrating a technology computer-aided design system by fitting simulation parameters of manufacturing process and electrical characteristic simulations, using first feature of commercial manufacturing process of first electronic device manufactured by first manufacturing facilities, and first electrical characteristic of the first electronic device; acquiring second feature of trial manufacturing process of second electronic device manufactured by second manufacturing facilities, and second electrical characteristic of the second electronic device; calculating simulation electrical characteristic of the second electronic device by substituting the second feature to the manufacturing process simulation corresponding to the trial manufacturing process; comparing the second electrical characteristic with the simulation electrical characteristic; and creating design specification of commercial manufacturing process of the second man

Abstract: The present invention provides a solution for interleaving data frames, in a semiconductor device manufacturing system in which the processing apparatus for conducting a process on any one of a semiconductor substrate and a thin film on a surface thereof; a self-diagnostic system for diagnosing a state of the processing apparatus; and a parameter fitting apparatus for maintaining a parameter of the self-diagnostic system when an inspection result of the semiconductor substrate having undergone the process has been determined to be correct, and for changing the parameter of the self-diagnostic system when the inspection result has been determined to be incorrect.

Abstract: A semiconductor design/fabrication system which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising: a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known; a chip information calculator which calculates a sum of the critical areas on each of the selected function blocks; an yield calculator which calculates an yield based on a calculation result of the chip information calculator and defect occurrence rate information of a chip fabrication line; a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of the yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and a combination selector which

Abstract: Critical location information is used for providing a critical location evaluation method for a semiconductor apparatus pattern. The critical location information includes coordinate information about the critical location and characteristic information indicating a thinning direction and a magnitude thereof at the critical location. Use of this evaluation method can accurately evaluate specification and analysis of thinning or a pattern which makes it difficult to pinpoint a critical location through the visual inspection.

Abstract: A semiconductor design/fabrication system which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising: a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known; a chip information calculator which calculates a sum of the critical areas on each of the selected function blocks; an yield calculator which calculates an yield based on a calculation result of the chip information calculator and defect occurrence rate information of a chip fabrication line; a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of the yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and a combination selector which

Abstract: A system for detecting dangerous process/pattern includes: an input data processing unit configured to convert input data into formatted data; a critical condition storage unit configured to store critical conditions for defect generation; a universal simulation unit configured to perform at least process simulation for the formatted data and output those result as dangerous process determination-formatted data; and a mask simulation unit configured to perform mask simulation for the formatted data and output those result as dangerous pattern determination-formatted data. In addition, the system includes a dangerous process determination unit configured to compare the dangerous process determination-formatted data and the critical conditions, and determine whether it is a dangerous process; and a dangerous pattern determination unit configured to compare the dangerous pattern determination-formatted data and the critical conditions, and determine whether or not it is a dangerous pattern.

Abstract: A system for trading a photo mask includes a purchase mediating section configured to exchange information with a mask buyer through a network, and a factory mediating section configured to exchange information with a mask factory. The system also includes a calculating section, a progress selecting section, and a manufacture instructing section. The calculating section calculates an estimated price and an estimated delivery date of a mask product with reference to line information about a manufacturing line in the mask factory, and price information about mask trading prices. The progress selecting section transmits the estimated price and the estimated delivery date to the mask buyer and allows the mask buyer to select whether to proceed with manufacture of the mask. The manufacture instructing section transmits the mask manufacture order to the mask factory, when proceeding with manufacture of the mask is selected.

Abstract: Critical location information is used for providing a critical location evaluation method for a semiconductor apparatus pattern. The critical location information includes coordinate information about the critical location and characteristic information indicating a thinning direction and a magnitude thereof at the critical location. Use of this evaluation method can accurately evaluate specification and analysis of thinning or a pattern which makes it difficult to pinpoint a critical location through the visual inspection.

Abstract: A polishing method and apparatus are provided for detecting the polishing end point of a semi-conductor wafer having a polishing film and a stopper film formed thereon. First driving means are provided having a first drive shaft for rotating a polishing plate and a polishing cloth thereon. Second driving means having a second rotatable drive shaft are also provided. Mounting means for mounting the semi-conductor wafer is adapted to be rotated by the second driving means for polishing the wafer. Energy supplying means for supplying prescribed energy to the semi-conductor wafer are also included. Finally, detecting means for detecting a polishing end point of the polishing film is included and detects a variation of the energy supplied to the semi-conductor wafer. Different types of energy can be utilized such as infrared light and a vibration wave.

Abstract: A compound semiconductor device such as HEMTs (High Electron Mobility Transistors), metal semiconductor field effect transistors, and the like includes a compound semiconductor substrate having an active region, an insulating film provided over the semiconductor substrate, source and drain electrodes provided on the active region, and a gate electrode located between the source and drain electrodes. In the structure, the gate electrode has a lower electrode portion for providing a Schottky barrier contact with the active region through an opening of the insulating film, and an upper electrode portion provided on the insulating film to extend toward only the drain electrode.

Abstract: A semiconductor device having a GaAs substrate and an ohmic electrode. An electrode pad is on part of the ohmic electrode and on part of the GaAs substrate outside the ohmic electrode. The electrode pad includes a first platinum film, a titanium film, a second platinum film, and a gold film which are sequentially deposited on one another. The first platinum film is thinner than each of the titanium film, second platinum film and gold film.

Abstract: A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.

Abstract: A Schottky gate electrode structure of a GaAs field effect semiconductor device comprises a Ti film having a thickness of 2 nm to 25 nm and provided adherently on a GaAs substrate including source and drain regions, and a refractory electrode film provided on the Ti film and formed of a material selected from W, Mo, Cr, Ta, Nb, V, Hf, Zr, nitrides of these metals, silicides of these metals, carbides of these metals, Ti-W alloys, WSixNy, TiNx, and TiSix. Adhesion of the refractory electrode film to the GaAs substrate is increased, and heat resisting properties of Schottky characteristics are improved according to the thin Ti film.

Abstract: There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 .ANG..

Abstract: A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film.

Abstract: Disclosed is a composite semiconductor device, comprising a composite substrate consisting of first and second semiconductor substrates, one surface of each of which is mirror-polished, so that the mirror-polished surfaces are bonded together.

Abstract: A method of manufacturing a semiconductor device wherein an insulating film of silicon dioxide is provided on the sidewalls of a gate electrode. This silicon dioxide film is used to define the length of the gate region during formation of the source and drain regions by ion implantation, and to accurately position the gate electrode relative to the source and drain regions.

Abstract: A method of manufacturing a GaAs FET is disclosed. In this manufacturing method, a protection film is formed on a GaAs substrate and a dummy gate electrode is formed thereon. A channel length setting film is isotropically formed on the dummy gate electrode to have a constant thickness. Then, an impurity is ion-implanted in the channel length setting film. Thereafter, the channel length setting film is removed. An etching preventive film is anisotropically formed along a substantially vertical direction with respect to the GaAs substrate. The dummy gate electrode is etched using the etching preventive film as a mask so as to form a first opening in the etching preventive film. Then, a second opening is formed in the region of the protection film corresponding to the region in which the dummy gate electrode was present. A gate electrode is formed to be in contact with the GaAs substrate through the first and second openings.

Abstract: An ion selective field-effect sensor selectively sensitive to a particular cation to be measured is disclosed. In the sensor is used a giant heterocyclic compound selectively forming a complex with the particular cation as an ion sensitive film provided on a surface of a field-effect semiconductor device.