Patents by Inventor Tatsuo Aramizu
Tatsuo Aramizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7970012Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: GrantFiled: February 27, 2009Date of Patent: June 28, 2011Assignee: Juniper Networks, Inc.Inventors: Tatsuhiko Amagai, Mikiharu Yamashita, Tatsuo Aramizu
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Publication number: 20090161694Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: ApplicationFiled: February 27, 2009Publication date: June 25, 2009Applicant: JUNIPER NETWORKS, INC.Inventors: Tatsuhiko AMAGAI, Mikiharu YAMASHITA, Tatsuo ARAMIZU
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Patent number: 7515610Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: GrantFiled: September 29, 2006Date of Patent: April 7, 2009Assignee: Juniper Networks, Inc.Inventors: Tatsuhiko Amagai, Mikiharu Yamashita, Tatsuo Aramizu
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Publication number: 20070025380Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: ApplicationFiled: September 29, 2006Publication date: February 1, 2007Applicant: JUNIPER NETWORKS, INC.Inventors: Tatsuhiko AMAGAI, Mikiharu YAMASHITA, Tatsuo ARAMIZU
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Patent number: 7130312Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: GrantFiled: September 24, 1999Date of Patent: October 31, 2006Assignee: Juniper Networks, Inc.Inventors: Tatsuhiko Amagai, Mikiharu Yamashita, Tatsuo Aramizu
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Publication number: 20030231633Abstract: Even when a communication failure happens to occur, the interrupted communication can be quickly recovered by a router apparatus. The router apparatus is comprised of: a plurality of routing tables into which new route information is stored every time route information is changed; a rewriting time saving unit for saving rewriting time information of the plurality of routing tables; a table switching unit for switching the plurality of routing tables; and a route processor unit for managing, for example, setting/rewriting/deleting the routing table based upon route information supplied by a network operator, or route information obtained by routing protocol.Type: ApplicationFiled: June 24, 2003Publication date: December 18, 2003Applicant: NEC CORPORATIONInventors: Tatsuo Aramizu, Tatsuhiko Amagai, Hiroshi Ikeda
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Patent number: 6625659Abstract: Even when a communication failure happens to occur, the interrupted communication can be quickly recovered by a router apparatus. The router apparatus is comprised of: a plurality of routing tables into which new route information is stored every time route information is changed; a rewriting time saving unit for saving rewriting time information of the plurality of routing tables; a table switching unit for switching the plurality of routing tables; and a route processor unit for managing, for example, setting/rewriting/deleting the routing table based upon route information supplied by a network operator, or route information obtained by routing protocol.Type: GrantFiled: January 18, 2000Date of Patent: September 23, 2003Assignee: NEC CorporationInventors: Tatsuo Aramizu, Tatsuhiko Amagai, Hiroshi Ikeda
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Patent number: 6515998Abstract: A table data retrieving apparatus comprises a plurality of tables in which a reference data is stored. Each table of said plurality of tables is allocated into any group of a plurality of groups. A management table stores a priority of said table. A data retrieving section selects a group based on the retrieving key by which the reference data is selected. The data retrieving section retrieves with the priority said table which is allocated into the selected group is stored.Type: GrantFiled: November 16, 1999Date of Patent: February 4, 2003Assignee: NEC CorporationInventors: Mikiharu Yamashita, Tatsuhiko Amagai, Tatsuo Aramizu
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Patent number: 6493356Abstract: A segment and reassembly system cooperates with a data processing system for various kinds of data processing on ATM cells accumulated in frame buffers, and supplies ATM cells to ISDN after completion of various kinds of data processing; wherein the segment and reassembly system has processing units connected through exclusive interfaces to engines incorporated in the data processing system, and the engines process the pieces of data stored in the frame buffers at high speed, thereby improving the throughput of the segmentation and reassembly system.Type: GrantFiled: January 7, 1999Date of Patent: December 10, 2002Assignee: NEC CorporationInventors: Tatsuo Aramizu, Tatsuhiko Amagai, Yasuo Hamakawa, Kazuhiko Isoyama
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Patent number: 5697800Abstract: The invention provides a multi-terminal connector for connecting a circuit board to another circuit board. The connector body consists of a first body 20 having a bar-like base part 21 and an uprightly and linearly projecting part 22 and a second body 40 having a slot 42 into which the projecting part 22 of the first body 20 fits. The cross-sectional shape of the slot 42 is such that the projecting part 22 of the first body 20 fits into the slot 42. The first body 20 is to be attached to a circuit board 100 and the second body 40 to another. The first body 20 has cavities 27 at intervals in the lengthwise direction, and each cavity 27 provides openings in side faces of the projecting part 22. A shaft 24 extends through the projecting part 22 of the first body 20, and contact blades 26 are fixed to the shaft 24 in the respective cavities 27 in the first body 20.Type: GrantFiled: April 25, 1996Date of Patent: December 16, 1997Assignee: NEC CorporationInventor: Tatsuo Aramizu