Abstract: A cache memory unit that preferentially stores specific lines at the cache memory, according to the program nature, dynamically changes the priority ranks of lines, and increases the cache memory hit rate. For this purpose, the lines to be accessed by a processor are divided into groups and definitions of the groups are set in a group definition table; a policy by which to store lines belonging to the groups into the cache memory is set in a policy table; and storing lines into the cache memory is executed, according to the group definitions and the policy of storing set in the tables.

Abstract: A multiprocessor system can reduce a broadcast for cache memory consistency control with memory access from an I/O device. The multiprocessor system is provided with a cache memory identifier or an owner tag, and a block length table for recording a memory write block length of the I/O device. The cache memory identifier records that the cache has an exclusive copy. The owner tag records that there is no cache memory having an exclusive copy. If there is an exclusive copy during read through the I/O device, a read request is issued to both a cache holding the copy and a memory. If it is recorded that the copy is not present, data are directly read from the memory. Moreover, when a write block length is recorded in the block length table during write, whole blocks are collected to issue a request for invalidation from the cache and the request is directly written to the memory after the invalidation is completed.

Abstract: Disclosed are a virtual computer system and method, wherein computer resources are automatically and optimally allocated to logical partitions according to loads to be accomplished by operating systems in the logical partitions and setting information based on a knowledge of workloads that run on the operating systems. Load measuring modules are installed on the operating systems in order to measure the loads to be accomplished by the operating systems. A manager designates the knowledge concerning the workloads on the operating systems through a user interface. An adaptive control module determines the alalocation ratios of the computer resources relative to the logical partitions according to the loads and the settings, and issues an allocation varying instruction to a hypervisor so as to thus instruct variation of allocations.

Abstract: A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each processing node for storing in parallel use status information indicating whether the resource is in exclusive use status. The computer system includes a plurality of request issue circuits, each being provided in each processing node, for issuing requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to the processing nodes and a plurality of status control circuits. Each status control circuit is provided in each processing node to update a corresponding register set depending on use status information and each request received at a corresponding node.

Abstract: A computer resource marketing system using LPAR (logical partitioning) technology that divides a computer resource into a plurality of logical partitions, including a lending server with a logical partition control unit 3 that designates at least one logical partition as a lendable partition, a client system that can borrow a logical partition in the lending server and submit processing to the logical partition, a resource database that stores lending conditions and certification information of logical partitions in the lending server, and a management server that searches the resource database based on a borrowing request from a client system, notifies the client system of a logical partition that meets the requirements of the borrowing request, and authorizes the client system to use the logical partition.

Abstract: A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.

Abstract: In order to execute a flow control and a congestion control in a hop-by-hop manner in a data communication among computers connected to different networks, in a data communication between a client A1 and a remote server B, a communication proxy of the remote server B is located in a local server A in an LAN to which the client A belongs. A communication packet to be routed to the remote server B is stolen (received) and passed to a transport layer. A TCP communication between the client A1 and the remote server B is divided into two; a communication between the client A1 and the communication proxy of the remote server B and a communication between the communication proxy of the remote server B and the remote server B.

Abstract: In order to execute a flow control and a congestion control in a hop-by-hop manner in a data communication among computers connected to different networks, in a data communication between a client Al and a remote server B, a communication proxy of the remote server B is located in a local server A in an LAN to which the client A belongs. A communication packet to be routed to the remote server B is stolen (received) and passed to a transport layer. A TCP communication between the client Al and the remote server B is divided into two; a communication between the client Al and the communication proxy of the remote server B and a communication between the communication proxy of the remote server B and the remote server B.

Abstract: A cache memory unit that preferentially stores specific lines into the cache memory, according to the program nature, dynamically changes the priority ranks of lines, and increases the cache memory hit rate, in which: the lines to be accessed by a processor are divided into groups and definitions of the groups are set in a group definition table; policy whereby to store lines belonging to the groups into the cache memory is set in a policy table; and storing lines into the cache memory is executed, according to the group definitions and the policy of storing set in the above tables.

Abstract: A multiprocessor system can reduce a broadcast for cache memory consistency control with memory access from an I/O device. The multiprocessor system is provided with a cache memory identifier or an owner tag, and a block length table for recording a memory write block length of the I/O device. The cache memory identifier has an exclusive copy. The owner tag records that there is no cache memory having an exclusive copy. If there is an exclusive copy during read through the I/O device, a read request is issued to both a cache holding the copy and a memory. If it is recorded that the copy is not present, data are directly read from the memory. Moreover, when a write block length is recorded in the block length table during write, whole blocks are collected to issue a request for invalidation from the cache and the request is directly written to the memory after the invalidation is completed.

Abstract: A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each of the processing nodes for storing in parallel use status information indicating whether the resource is in exclusive use status or not. The computer system can also include a plurality of request issue circuits, each being provided in each of the processing nodes, for issuing individually requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to all of the processing nodes in the serialized order and a plurality of status control circuits.

Abstract: Collation Fourier image data (FIG. 1D) FB generated by performing the two-dimensional discrete Fourier transform (DFT) for the image data (FIG. 1C) of a collation pattern is synthesized with registration Fourier image data (FIG. 1B) generated by performing the two-dimensional DFT for the image data of a registration pattern. After amplitude suppression processing is performed for the resultant data, two-dimensional DFT is performed. A correlation peak is extracted from a correlation component area which appears in the synthesized Fourier image data (FIG. 1E) for which the two-dimensional DFT has been performed. A predetermined area including this correlation peak is then masked (FIG. 1F). The two-dimensional DFT is performed for the masked synthesized Fourier image data, and amplitude restoration processing is performed for the data. The resultant data is re-synthesized with the registration Fourier image data FA, and the two-dimensional IDFT is performed for the synthesized data.

Abstract: This invention provides dynamic balance of the traffic among data processing devices interconnecting networks and thereby improve the networking performance. For network traffic flowing between a first network and a second network, the traffic is distributed among the data processing devices that act as routers according to the traffic amount. An algorithm for balancing the traffic is used to select appropriate data processing devices as routers.

Abstract: A processor for a multiprocessor system, such as a parallel processor system, connected to a network has a sending unit and a receiving unit for transferring and receiving data to and from the network as well as a receive cache and a main cache. When data is received from the network, it is determined whether a hit or miss occurs to the main cache and receive cache, respectively. If a hit to the receive cache occurs, then the receive cache controller stores the data directly in the receive cache as it is received. When a hit to the main cache occurs, an intercache transfer is executed for transferring the hit block in the main cache to the receive cache so that the data can be stored in the receive cache. When an instruction processor requests access to data held in the receive cache, the data is retrieved to the instruction processor and at the same time transferred to a main cache.

Abstract: To reduce an overhead of the interrupt on a processor associated with packet send and receive control in a network, a packet send command chaining unit is provided. Based on the control field in each packet send command, a send node controls an interrupt request to the processor in the packet level and sends a packet set with the control information to a receive node. Based on the control field in the received data packet, the receive node controls a receive circuit interrupt request, thereby reducing the number of times the interrupt on the instruction processor is caused for each packet send and receive operation.

Abstract: In a pattern processing apparatus, a registration data preparation unit performs two-dimensional discrete Fourier transform of image data of a registration pattern to prepare registration Fourier image data. A collation data preparation unit performs two-dimensional discrete Fourier transform of image data of a collation pattern to prepare collation Fourier image data. A data synthesizing unit synthesizes the registration Fourier image data with the collation Fourier image data, both of which consist of phase and amplitude information, to output first synthesized Fourier image data. An image processing unit performs Fourier transform of the first synthesized Fourier image data to output second synthesized Fourier image data representing intensities of correlation components.

Abstract: In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

Abstract: In a method of transferring packets in a network for a parallel processor system handling a one-to-one transfer packet to be transferred from a processor to another processor and a broadcast packet to be transferred from a processor to a plurality of other processors, a transfer request of a broadcast packet is preferentially selected and a check is made to detect whether or not a plurality of processors specified as receivers are in a state in which the packet can be received. The broadcast packet is transferred to the processors found to be in the state in which the packet can be received. The packet transfer is delayed for the other processors in a state in which the packet cannot be received. Namely, only when the state of the processors is changed to the state in which the packet can be received, the broadcast packet is transferred thereto.

Abstract: In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks.

Abstract: In order to reduce load at a resource managing node for exclusive control of a shared resource, each node has a group of lock state registers each corresponding to one of the nodes. Before one node issues a lock request to a resource managing node, the node checks the register group to see if the resource managing node is unlocked. With the target node found to be accessible, the access requesting node sends to a broadcast message exchange circuit a broadcast request message including a lock request regarding the resource managing node. The broadcast message exchange circuit receives such broadcast request messages from access requesting nodes, and changes them serially into broadcast messages for broadcast to all nodes. Of these broadcast messages, the first message received by each node is processed by its lock control circuit so that the lock request in that message is allowed to lock the resource managing node.