Abstract: A system for managing sales of goods for vending machines includes a goods control center, a plurality of vending machines, and terminal computers equipped in the respective vending machines. The goods control center includes a host computer for preparing digital data signals as control instructions, and a frequency moderation sub-carrier broadcasting facility as a transmission facility for outputting the digital data signals. Each vending machine has a receiving facility for receiving the digital data signals from the goods control center, and a responding facility. Each terminal computer receives the digital data signals and selectively extracts the digital data as the control instructions necessary for the vending machine to thereby store the digital data necessary for the vending machine in a memory.

Abstract: An FM multiple radio broadcasting receiver includes a data group number and data packet number derivation circuit by which a data group number and a data packet number included in a prefix of FM subcarrier data are derived. A first random number generator generates a first random number on the basis of the data group number, the data packet number and scramble key data which is outputted from a scramble key generation circuit, and sets the first random number in a second random number generator as its initial value. Therefore, it is possible to appropriately scramble or descramble with using packet structure of the FM subcarrier data.

Abstract: A scrambling key is generated from demodulated and error-corrected FM demodulation data for use in descrambling. During this process, if error correction has not been normally conducted to an object data packet, a subsequent descrambling operation is not executed to that data packet. In addition, a descrambling operation is not carried out if the object data packet is a parity packet.

Abstract: In a packet analyzing circuit, first and second key data are detected and stored in respective first and second key data registers. First and second key generation circuits generate first and second keys from the first and second key data. An exclusive OR operation is carried out to both keys so as to generate a scrambling key. Using the scrambling key as an initial value, a random number generator generates a PN code used for scrambling, so that scrambled data is descrambled by adding the PN code to the data. The first key generation circuit, which receives a control signal CON from a timing generation circuit, is controlled by the control signal CON such that a scrambling key is generated only when the random number generator needs an initial value.

Abstract: In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circuit outputs a pseudo-random binary sequence on the basis of a data group number and a data packet number outputted from the shift register and key data previously extracted by a key data fetch circuit. When a second comparison circuit detects that block data in the data packet is inputted in the shift register, an exclusive OR circuit exclusively ORs the pseudo-random binary sequence with receive data, so that decoded data is inputted in the shift register.

Abstract: A bi-phase signal is output from BPSK demodulator; by a pair determining circuit and a clock reproducing circuit, a clock signal corresponding to a former half bit of two half bits constituting a data pair of the bi-phase signal is reproduced; a carrier pulse immediately following the clock signal is generated by a carrier extracting circuit; using the carrier pulse and a carrier pulse obtained by delaying the pulse signal by a half bit period as a sampling clock, the bi-phase signal is subjected to AD conversion by AD converting circuit; two AD converted data values different in time are input to a subtraction circuit, and a result of subtraction between data pairs of bi-phase signals is obtained; thus sign of a bi-phase signal is determined.

Abstract: A costas loop includes a comparator, and a BPSK-modulated signal which is converted into a binary signal by the comparator is latched by a D-FF according to an oscillation signal from a VCO. An output of the D-FF becomes a demodulated signal. On the other hand, a phase-difference between the BPSK-modulated signal and the oscillation signal is detected by a phase-comparator, and the phase-difference is applied to the VCO via a loop filter. An oscillation frequency of the VCO is thus controlled according to a phase-comparison result.

Abstract: A spread spectrum communictdion system includes a transmitter and a receiver, and an on-off keying signal is inputted to the transmitter. A carrier signal is modulated by the on-off keying signal, and a spread spectrum signal is produced by multiplying a modulated signal by a first PN code which is repetition of 3-bit data. The spread spectrum signal is transmitted through a transmission antenna. In the receiver, a second PN code which is repetition of 4-bit data larger than the first PN code by 1 bit is generated. Therefore, a phase of the second PN code becomes coincident with a phase of the first PN code every 12 bits. Then, a spread spectrum demodulation is performed by multiplying a received spread spectrum signal by the second PN code to reproduce the carrier signal being modulated by the on-off keying signal. The on-off keying signal is restored by envelope-detecting a reproduced carrier signal.

Abstract: A spread spectrum signal demodulation circuit includes a multiplier which multiplies an input spread spectrum signal by a demodulation PN code, and a demodulation PN code generator generates the demodulation PN code by utilizing an oscillation signal from a VCO as a clock signal thereof. An output of the multiplier is given to a bandpass filter and an output of which is integrated by an integration circuit. A first integrated value for a first time is compared with a second integrated value for a second time later than the first time and, in accordance with a comparison result, a frequency of the oscillation signal of the VCO is changed so that the demodulation PN code is synchronized with a modulation PN code included in the input spread spectrum signal.

Abstract: An auto focus circuit for a video camera comprises an A-D converting circuit (7) for converting to a digital amount a high frequency component absolute value output of a luminance signal in a sampling area for focusing. The A-D converting circuit (7) is connected so that the high frequency component absolute value output of a luminance signal is directly converted to a digital amount. Then, the signal converted to a digital amount is added in an integrating circuit (12) for each field and the signal amount in one field and the signal amount in the coming one field ahead of it or behind it are compared in a comparing circuit (10) so that the output of comparison serves for control of focusing. Thus, addition processing of the high frequency component of the luminance signal, that is, averaging processing is performed digitally in the integrating circuit (12).

Abstract: An auto focus circuit for a video camera comprises an A-D converting circuit (7) for converting to a digital amount a high frequency component absolute value output of a luminance signal in a sampling area for focusing. The A-D converting circuit (7) is connected so that the high frequency component absolute value output of a luminance signal is directly converted to a digital amount. Then, the signal converted to a digital amount is added in an integrating circuit (12) for each field and the signal amount in one field and the signal amount in the coming one field ahead of it or behind it are compared in a comparing circuit (10) so that the output of comparison serves for control of focusing. Thus, addition processing of the high frequency component of the luminance signal, that is, averaging processing is performed digitally in the integrating circuit (12).