Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

Abstract: The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.

Abstract: A plug includes a plug housing and a metal terminal group. The metal terminal group includes a mating electrode group on the first end side thereof and a connection electrode group on the second end side, the mating electrode group including mating electrode sections that are disposed with an insulating resin interposed therebetween and are to be in contact with the contacts of a mating jack, the connection electrode group including connection electrode sections that are disposed with an insulating resin interposed therebetween and are connected to the electrodes of a connection member. The mating electrode sections are disposed coaxially with an axis P of the plug, and at least two of the connection electrode sections are disposed around the axis P so as to surround the axis P side by side.

Abstract: A plug includes a plug housing and a metal terminal group. The metal terminal group includes a mating electrode group on the first end side thereof and a connection electrode group on the second end side, the mating electrode group including mating electrode sections that are disposed with an insulating resin interposed therebetween and are to be in contact with the contacts of a mating jack, the connection electrode group including connection electrode sections that are disposed with an insulating resin interposed therebetween and are connected to the electrodes of a connection member. The mating electrode sections are disposed coaxially with an axis P of the plug, and at least two of the connection electrode sections are disposed around the axis P so as to surround the axis P side by side.

Abstract: The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.

Abstract: The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.

Abstract: Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.

Abstract: A power supply step-down circuit is adapted to a semiconductor integrated circuit having a first operation mode and a second operation mode having a smaller current consumption than the first operation mode. The power supply step-down circuit includes a first step-down circuit activated only during the first operation mode to step down an input power supply voltage to an output voltage, a second step-down circuit provided integrally with the first step-down circuit and activated only during the second operation mode to step down the input power supply voltage to an output voltage, an output terminal to output the output voltage of one of the first and second step-down circuits that is activated, and an output circuit to maintain the output voltage that is output from the output terminal lower than the input power supply voltage for a first predetermined time when an operation mode makes a transition from the first operation mode to the second operation mode.

Abstract: A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

Abstract: A power supply step-down circuit is adapted to a semiconductor integrated circuit having a first operation mode and a second operation mode having a smaller current consumption than the first operation mode. The power supply step-down circuit includes a first step-down circuit activated only during the first operation mode to step down an input power supply voltage to an output voltage, a second step-down circuit provided integrally with the first step-down circuit and activated only during the second operation mode to step down the input power supply voltage to an output voltage, an output terminal to output the output voltage of one of the first and second step-down circuits that is activated, and an output circuit to maintain the output voltage that is output from the output terminal lower than the input power supply voltage for a first predetermined time when an operation mode makes a transition from the first operation mode to the second operation mode.

Abstract: A reference voltage generation circuit has transistors generating a PTAT current that increases in proportion to temperature, a transistor generating a CTAT current that decreases in proportion to temperature, a first variable resistor adjusting an output voltage, a transistor supplying the PTAT current to the first variable resistor via a first switch, a transistor supplying the CTAT current to the first variable resistor via a second switch, and a second variable resistor adjusting the CTAT current. The first switch is on in first and third operation modes and off in a second operation mode. The second switch is on in the first and second operation modes and off in the third operation mode. Switching the operation modes realizes independently outputting a PTAT voltage or a CTAT voltage. Independently adjusting the voltages makes it possible to correct output reference voltage of the reference voltage generation circuit accurately at low cost.

Abstract: The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.

Abstract: A reference voltage generation circuit has transistors generating a PTAT current that increases in proportion to temperature, a transistor generating a CTAT current that decreases in proportion to temperature, a first variable resistor adjusting an output voltage, a transistor supplying the PTAT current to the first variable resistor via a first switch, a transistor supplying the CTAT current to the first variable resistor via a second switch, and a second variable resistor adjusting the CTAT current. The first switch is on in first and third operation modes and off in a second operation mode. The second switch is on in the first and second operation modes and off in the third operation mode. Switching the operation modes realizes independently outputting a PTAT voltage or a CTAT voltage. Independently adjusting the voltages makes it possible to correct output reference voltage of the reference voltage generation circuit accurately at low cost.

Abstract: A band gap circuit includes a voltage generating circuit, and a first and a second switched capacitor circuits (SCC). Operational amplifier in the first and the second SCC are connected though a coupling capacitor. Capacitance of the coupling capacitor is smaller than that of a feedback capacitor in the first SCC. A PTAT voltage is obtained by multiplying a thermal voltage by a coefficient determined based on capacitances of input capacitors and feedback capacitors in each of the first and the second SCC, and the coupling capacitor. The voltage generating circuit generates a forward bias voltage that has a negative temperature-dependency at a p-n junction. The PTAT voltage is added to the forward bias voltage to generate a reference voltage independent of temperature.

Abstract: Included are a first unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the first analog signal, a second unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the second analog signal, a first switch connecting the first unit to an output side of the second unit, a comparator comparing a differential value between the first analog signal and the second analog signal with a differential value between the comparison signal of the first DAC and an output signal of the second DAC, and an electric potential control circuit controlling fluctuations in electric potentials of the first analog terminal and the second analog terminal.

Abstract: Included are a first DAC taking in and retaining sample data of a first analog signal and generating a comparison signal serving as an object of comparison with the first analog signal, a second DAC taking in and retaining sample data of a second analog signal and generating a comparison signal as an object of comparison with the second analog signal, a first switch connecting the first digital-to-analog converter to an output side of a second digital converter in a openable/closable manner, a comparator comparing, when the first switch is opened, a differential value between the first analog signal and the second analog signal with a differential value between an output signal of the first DAC and an output signal of the second DAC, and an electric potential control circuit controlling fluctuations in electric potentials of a first analog terminal and a second analog terminal.