Patents by Inventor Tatsuo Migita

Tatsuo Migita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929332
    Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: March 12, 2024
    Assignee: Kioxia Corporation
    Inventors: Soichi Homma, Tatsuo Migita, Masayuki Miura, Takeori Maeda, Kazuhiro Kato, Susumu Yamamoto
  • Publication number: 20230411330
    Abstract: A semiconductor device according to the present embodiment includes an insulation member, a columnar electrode, a member, and an electrode pad. The insulation member has a first face. The columnar electrode penetrates the insulation member in a direction approximately perpendicular to the first face. The columnar electrode has a columnar electrode member and a first metal layer of at least one layer which covers an outer circumference of the columnar electrode member and which extends until becoming exposed from the first face. The member is provided on the first face and is arranged so as to overlap with at least a part of the first metal layer that is exposed from the first face as viewed from a direction approximately perpendicular to the first face. The electrode pad is provided on the first face so as to cover the member and is electrically connected to the columnar electrode member.
    Type: Application
    Filed: September 8, 2022
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Masatoshi SHOMURA, Tatsuo MIGITA
  • Publication number: 20230307415
    Abstract: According to one embodiment, a semiconductor device includes a base substrate with an interconnection layer and a plurality of chips stacked on the base substrate. A protective film is between each adjacent pair of chips in the plurality of chips stacked on the base substrate and on side surfaces of at least each chip in the plurality other than an uppermost chip in the stacked plurality of chips. A lowermost chip in the stacked plurality of chips has a metal pad electrically connected to the interconnection layer. Each chip in an adjacent pair of chips in the plurality of chips stacked on the base substrate has an electrode contacting an electrode of the other chip in the adjacent pair.
    Type: Application
    Filed: August 30, 2022
    Publication date: September 28, 2023
    Inventors: Satoshi HONGO, Tatsuo MIGITA, Gen TOYOTA
  • Publication number: 20230200092
    Abstract: A storage wafer includes: a first semiconductor; a first element layer provided on the first semiconductor; a first pad provided on a first region of the first element layer; a second pad provided on a second region of the first element layer; an adhesive film provided on the second region; a second semiconductor provided on the adhesive film; a second element layer provided on the second semiconductor; and a third pad provided on the second element layer. The first element layer includes: first and second memory chip units coupled to the first and second pads, respectively. The second element layer includes an element coupled to the third pad and isolated from both the first and second pad.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 22, 2023
    Applicant: Kioxia Corporation
    Inventor: Tatsuo Migita
  • Publication number: 20230101002
    Abstract: A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.
    Type: Application
    Filed: March 14, 2022
    Publication date: March 30, 2023
    Applicant: Kioxia Corporation
    Inventors: Gen TOYOTA, Satoshi HONGO, Tatsuo MIGITA, Susumu YAMAMOTO, Tsutomu FUJITA, Eiichi SHIN, Yukio KATAMURA, Hideki MATSUSHIGE, Kazuki TAKAHASHI
  • Patent number: 11398376
    Abstract: A manufacturing method of an embodiment of a semiconductor device, the manufacturing method includes: heating a second layer of a first member including a first layer, the second layer, and a third layer, in which the first layer includes a support layer, the second layer includes a compound containing carbon and at least one element selected from the group consisting of silicon and metals, the third layer includes a semiconductor layer and/or a wiring layer, and the second layer is located between the first layer and the third layer, and obtaining a second member in which a carbonaceous material layer is formed on a surface of the second layer and/or a carbonaceous material region is formed inside the second layer; and cleaving the second member from the carbonaceous material layer or the carbonaceous material region, and obtaining a third member including the third layer.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: July 26, 2022
    Assignee: Kioxia Corporation
    Inventor: Tatsuo Migita
  • Publication number: 20220013477
    Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.
    Type: Application
    Filed: March 2, 2021
    Publication date: January 13, 2022
    Applicant: Kioxia Corporation
    Inventors: Soichi HOMMA, Tatsuo MIGITA, Masayuki MIURA, Takeori MAEDA, Kazuhiro KATO, Susumu YAMAMOTO
  • Publication number: 20210280416
    Abstract: A manufacturing method of an embodiment of a semiconductor device, the manufacturing method includes: heating a second layer of a first member including a first layer, the second layer, and a third layer, in which the first layer includes a support layer, the second layer includes a compound containing carbon and at least one element selected from the group consisting of silicon and metals, the third layer includes a semiconductor layer and/or a wiring layer, and the second layer is located between the first layer and the third layer, and obtaining a second member in which a carbonaceous material layer is formed on a surface of the second layer and/or a carbonaceous material region is formed inside the second layer; and cleaving the second member from the carbonaceous material layer or the carbonaceous material region, and obtaining a third member including the third layer.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 9, 2021
    Applicant: Kioxia Corporation
    Inventor: Tatsuo MIGITA
  • Patent number: 10985006
    Abstract: An electrolytic plating apparatus includes a plating tank that is filled with plating liquid; a moving mechanism configured to vertically move a processing target substrate in a direction normal to a surface of the plating liquid; a seal member that is disposed at a peripheral edge portion of a processing target surface of a processing target substrate and is configured to seal the plating liquid to a center side of the processing target surface when the processing target substrate is immersed in the plating tank; and a contact member that is separated from the seal member and is electrically connected to the processing target surface.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumito Shoji, Tatsuo Migita, Masahiko Murano
  • Patent number: 10971400
    Abstract: A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masahiko Murano, Fumito Shoji, Tatsuo Migita, Ippei Kume
  • Publication number: 20200273749
    Abstract: A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.
    Type: Application
    Filed: September 2, 2019
    Publication date: August 27, 2020
    Inventors: Masahiko MURANO, Fumito SHOJI, Tatsuo MIGITA, Ippei KUME
  • Patent number: 10720410
    Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 21, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuo Migita, Koji Ogiso
  • Publication number: 20190295836
    Abstract: An electrolytic plating apparatus includes a plating tank that is filled with plating liquid; a moving mechanism configured to vertically move a processing target substrate in a direction normal to a surface of the plating liquid; a seal member that is disposed at a peripheral edge portion of a processing target surface of a processing target substrate and is configured to seal the plating liquid to a center side of the processing target surface when the processing target substrate is immersed in the plating tank; and a contact member that is separated from the seal member and is electrically connected to the processing target surface.
    Type: Application
    Filed: August 27, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Fumito SHOJI, Tatsuo MIGITA, Masahiko MURANO
  • Patent number: 10312143
    Abstract: A semiconductor device includes a semiconductor substrate, a metal member, and a metal oxide film. The semiconductor substrate is provided with a through-hole that passes through the semiconductor substrate from one surface to another surface opposite to the one surface. The metal member is provided in the through-hole, and includes a cavity therein defined by an internal surface. The metal oxide film coats the internal surface.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuo Migita, Koji Ogiso
  • Publication number: 20190006324
    Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.
    Type: Application
    Filed: September 7, 2018
    Publication date: January 3, 2019
    Inventors: Tatsuo MIGITA, Koji OGISO
  • Patent number: 10115703
    Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuo Migita, Koji Ogiso
  • Patent number: 10115689
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode, a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface, and a first bump comprising a bump diameter of 30 ?m or less connected to the first bump electrode. The width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: October 30, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Taku Kamoto, Tatsuo Migita, Shinya Watanabe
  • Patent number: 10083893
    Abstract: According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: September 25, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koji Ogiso, Kazuyuki Higashi, Tatsuo Migita
  • Publication number: 20180233468
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode, a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface, and a first bump comprising a bump diameter of 30 ?m or less connected to the first bump electrode. The width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.
    Type: Application
    Filed: September 4, 2017
    Publication date: August 16, 2018
    Inventors: Taku KAMOTO, Tatsuo MIGITA, Shinya WATANABE
  • Patent number: 9941165
    Abstract: A semiconductor manufacturing method includes forming a first metal film on a semiconductor wafer by plating, ejecting liquid from a washer bar spaced from the wafer while rotating at least one of the washer and the semiconductor, and forming a second metal film on the first metal film. A plurality of nozzles are located on the washer bar and displaced from the position of the washer bar opposed to the center of the wafer, and a greater number of nozzles are adjacent the peripheral area of the semiconductor wafer than the central area of the semiconductor wafer. The nozzles in the peripheral area of the wafer eject the washing liquid in a direction inclined from the direction of the washer bar, and a nozzle arranged on the central area of the one main surface of the semiconductor wafer ejects the washing liquid towards the center position of the semiconductor wafer.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuo Migita, Fumito Shoji, Koji Ogiso