Abstract: In a system for measuring a time difference of arrival of signals for positioning, an accurate time difference is measured by a receiver which is reduced in power consumption, size, and cost. The system comprises a node (under measurement) for transmitting a positioning signal, a reference station for transmitting a reference signal, and a plurality of access points for receiving the positioning signal and reference signal, and a server connected to the plurality of access points through a network. Each of the plurality of access points measures a time difference between the reception of the positioning signal and the reception of the reference signal, and a frequency deviation from the reference station, using a clock signal and a signal for shifting the clock signal, and the server calculates the position of the node based on the measured time difference and frequency deviation.

Abstract: With the objective of enhancing receiving performance of a receiver with respect to pulse signals spread by spread codes, the receiver comprises an RF front-end section which performs amplification, an AD converter section which AD-converts signals outputted from the RF front-end section, a baseband section which inversely spreads the output of the AD converter section and performs signal detection and demodulation thereon, a reception environment measuring section which measures reception environment using the input signals of the baseband section, and a parameter setting section which sets parameters for respective parts on the basis of signals outputted from the reception environment measuring section. The parameter setting section sets the parameters for the respective parts to the optimum according to the environmental condition measured by the reception environment measuring section.

Abstract: A traffic shaping method and apparatus which prevents a violation to a peak rate caused by a fluctuation of a flow of ATM cells outputted from a frame crossing over circuit is provided. A traffic shaping apparatus which includes a traffic shaper for shaping input ATM cells and a frame crossing over circuit for crossing over the frame period of output ATM cells outputted from the traffic shaper is provided with an output rate supervision circuit which supervises the transmission rate of output ATM cells and transmits, if it detects an overhead inserted in the output ATM cells, a back pressure to the traffic shaper to stop the traffic shaping operation of the traffic shaper. However, if the transmission average rate exhibits a drop, then the output rate supervision circuit transmits output rate information to the traffic shaper so that the traffic shaper may perform its traffic shaping operation until the transmission average rate rises to an allowable maximum rate set in advance.

Abstract: An asynchronous (ATM) exchange system comprises a plurality of input buffers each for receiving data cells from an input cell highway to temporarily store the data cells, a plurality of output buffers each for temporarily storing data cells to transmit the data cells to an output cell highway, and an array of ATM switches each for transferring data cells from one of the input buffers to one of the output buffers. The amount of data cells stored in each output buffer is monitored by an output buffer monitor and used for controlling the transfer rate of the data cells from each input buffers, thereby increasing durability of the ATM exchange system against a burst signal or buffer congestion.

Abstract: The input/output buffer type ATM switch capable of traffic control depending on the traffic type at the time of cell congestion is provided. There are provided an input buffer memory and an output buffer memory for storing cells at each of a plurality of input ports and a plurality of output ports. Each of the input buffer memories is provided with queues corresponding to each of the output ports, logically independent for traffic types and sharing a memory area. Each of the output buffer memories is provided with queues logically independent for traffic types and sharing a memory area, and outputs an overflow signal corresponding to a remaining memory capacity against each of the input buffer memories. Cell transmission from the input buffer memories is controled in response to a remaining memory capacity and the traffic type indicated by the overflow signal.

Abstract: An ATM cell switching apparatus which prevents degradation of user cells in the ATM switch and preserve the quality of control cells, even upon increase in the control cells. Control cell discriminator 2.sub.1 discriminates whether the cells on the input cell highways 1.sub.1 are control cells or user cells, and output control cell dropping instruction signal 3.sub.1 when the cells are discriminated as control cells. Control cell dropper 4.sub.1 distributes the user cells onto the cell highways 5.sub.1 and the control cells onto the input control cell highway 6.sub.1. Control cell processing unit 8 performs a termination of the control cells and processes necessary operation ralating to the control cells. The control cells to be output are temporarily stored in the control cell FIFO 13.sub.1, and inserted into an idle cell position in the switch output cell highway 10.sub.1 when an idle cell is appeared. If no idle cell is available, the idle cell output instruction signal 14.sub.

Abstract: Supplied with first and second signals from first and second control units (19, 29), first and second reading units (17, 27).read first and second readout ATM signals from first and second primary memory units (15, 25) which memorize an ATM signal (11). The second control unit produces the second-reading signal when a predetermined interval lapses after supplied with a first reading start signal from the first control unit. A first processing unit (21) processes the first readout ATM signal into a first STM signal and a first processed content signal. A second processing unit (31) processes, in response to the first processed content signal, the second readout ATM signal into a second STM signal. An output reading unit (35) read first and second output STM signals at the same time from first and second secondary memory units (23, 33) which memorize the first and the second readout STM signals.

Abstract: An assembly/disassembly system containing a cell assembly and a cell disassembly, each having one buffer memory with its memory area logically divided into a plurality of data areas (banks). The cell assembly receives TDM data to assemble ATM cells by storing the TDM data into the respective banks according to the virtual channels. When one of the banks stores the TDM data in the payload length of an ATM cell, a new bank (unused bank) is specified to store the TDM data successively. An ATM cell is formed by using the data read out from the bank where the TDM data is stored in the payload length of an ATM cell. The cell disassembly receives ATM cells from the ATM highway to disassemble the ATM cells into TDM data by using the buffer memory. The payload of a received cell is stored into an unused bank. A chain of the bank addresses each storing the payload of the received ATM cell is formed for each virtual channel of received ATM cells.