Patents by Inventor Tatsuo Nishimaki

Tatsuo Nishimaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7218538
    Abstract: A power source device is provided including a boosting circuit for stepping-up an input voltage to a desired output voltage, a starter circuit for starting the boosting circuit in a starting period thereof, and a drive circuit for driving the boosting circuit as a substitute for the starter circuit after the output voltage of the boosting circuit becomes equal to or greater than a predetermined level. The starter circuit comprises a starter signal generation circuit for generating a starter signal which on/off controls a MOS transistor used for stepping-up in the boosting circuit, and a determining/controlling circuit which detects whether or not a monitor voltage in the boosting circuit is equal to or greater than a predetermined level while the MOS transistor is in the on-state, and inhibits outputting if the starter signal if the monitor voltage is equal to or greater than the predetermined level.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 15, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuo Nishimaki
  • Patent number: 6998824
    Abstract: A power supply circuit includes a DC—DC conversion circuit including a high side transistor and a low side transistor connected in series between a power supply voltage and a reference potential and producing a voltage as PWM controlled output which is obtained by turning “on” and “off” each of the transistors with each PWM signal. The power supply circuit also includes a PWM circuit and output driver that detects a level of an intermediate node potential at a junction point of the high side transistor and the low side transistor after turning “off” the high side transistor, and turning “on” the low side transistor when the intermediate node potential becomes below or equal to a predetermined potential.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: February 14, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuo Nishimaki
  • Patent number: 6927986
    Abstract: A PWM circuit is provided that is capable of PWM control with duties in a range of 0-100%, and that is also capable of high-speed responses.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: August 9, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuo Nishimaki
  • Publication number: 20050168163
    Abstract: A power source device is provided including a boosting circuit for stepping-up an input voltage to a desired output voltage, a starter circuit for starting the boosting circuit in a starting period thereof, and a drive circuit for driving the boosting circuit as a substitute for the starter circuit after the output voltage of the boosting circuit becomes equal to or greater than a predetermined level. The starter circuit comprises a starter signal generation circuit for generating a starter signal which on/off controls a MOS transistor used for stepping-up in the boosting circuit, and a determining/controlling circuit which detects whether or not a monitor voltage in the boosting circuit is equal to or greater than a predetermined level while the MOS transistor is in the on-state, and inhibits outputting if the starter signal if the monitor voltage is equal to or greater than the predetermined level.
    Type: Application
    Filed: November 19, 2004
    Publication date: August 4, 2005
    Inventor: Tatsuo Nishimaki
  • Patent number: 6870354
    Abstract: A power source circuit includes a CMOS inversion circuit including a P-channel transistor and an N-channel transistor connected in series between a power source voltage and a reference potential, the transistors being alternately turned “on” or “off” by a PWM signal input to a gate of each transistor with an “on” period of the transistors being controlled, and being capable of outputting a D.C. voltage to a load via a stabilized capacitance. The circuit also includes a detection circuit outputting a detection signal showing a state where an intermediate node potential at a connection point of the P-channel transistor and the N-channel transistor surpasses the reference potential after undershooting to a level lower than the reference potential when the N-channel transistor is turned “on” during the “off” period of the P-channel transistor. An error amplifier is provided that obtains an error signal by comparing an output from the CMOS inversion circuit with a predetermined reference voltage value.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: March 22, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuo Nishimaki
  • Publication number: 20040104714
    Abstract: A power source circuit includes a CMOS inversion circuit including a P-channel transistor and an N-channel transistor connected in series between a power source voltage and a reference potential, the transistors being alternately turned “on” or “off” by a PWM signal input to a gate of each transistor with an “on” period of the transistors being controlled, and being capable of outputting a D.C. voltage to a load via a stabilized capacitance. The circuit also includes a detection circuit outputting a detection signal showing a state where an intermediate node potential at a connection point of the P-channel transistor and the N-channel transistor surpasses the reference potential after undershooting to a level lower than the reference potential when the N-channel transistor is turned “on” during the “off” period of the P-channel transistor.
    Type: Application
    Filed: July 18, 2003
    Publication date: June 3, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Tatsuo Nishimaki
  • Publication number: 20040080303
    Abstract: A power supply circuit includes a DC-DC conversion circuit including a high side transistor and a low side transistor connected in series between a power supply voltage and a reference potential and producing a voltage as PWM controlled output which is obtained by turning “on” and “off” each of the transistors with each PWM signal. The power supply circuit also includes a PWM circuit and output driver that detects a level of an intermediate node potential at a junction point of the high side transistor and the low side transistor after turning “off” the high side transistor, and turning “on” the low side transistor when the intermediate node potential becomes below or equal to a predetermined potential.
    Type: Application
    Filed: July 18, 2003
    Publication date: April 29, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Tatsuo Nishimaki
  • Publication number: 20030214272
    Abstract: A PWM circuit is provided that is capable of PWM control with duties in a range of 0-100%, and that is also capable of high-speed responses.
    Type: Application
    Filed: March 26, 2003
    Publication date: November 20, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Tatsuo Nishimaki
  • Publication number: 20020050936
    Abstract: A self-powered USB machine. A power control switch 23 is installed in a main power circuit 21 of the USB machine. By detecting whether a voltage occurs at a +5V power terminal of a USB port, the power control switch 23 is turned on or off. A pull-up resistor 17 is connected to a switch 18 in series. And, the pull-up switch 18 is turned on or off after the power control switch 23 is turned on or off. Thereby, the power consumption is reduced.
    Type: Application
    Filed: September 24, 2001
    Publication date: May 2, 2002
    Inventors: Tetsuya Kato, Tatsuo Nishimaki, Kazuhiro Sendo
  • Patent number: 5384732
    Abstract: A semiconductor device in which not only mask options of a mask ROM can be provided in the form of a PROM but the chip size can be reduced, and an electronic appliance using the same. The semiconductor device comprises a nonvolatile storage device (12) writable electrically, and switching circuits (18, 20) controlled on the basis of data stored in the nonvolatile storage device to perform wiring switching. Because wirings A, B1 and B2 are switched on the basis of data stored in the nonvolatile storage device, for example, optional functions of a one-chip micro computer can be provided in the form of a PROM by using the wiring switching.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: January 24, 1995
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuo Nishimaki
  • Patent number: 5323171
    Abstract: A power source circuit consisting of a combination of a constant-voltage circuit (1) and a voltage raising/lowering circuit (2) which produces a plurality of output voltages by raising or lowering the output of the constant-voltage circuit. When a change in the power source voltage or the presence or absence of a heavy load is detected that information is supplied as a control mode signal to both the circuit (1) and circuit (2). For instance, when the power source voltage is reduced or when a heavy load is driven, the output voltage of the circuit (1) lowered and instead the rate of change in the output voltage of the circuit (2) is adjusted so that the output voltage may eventually become the same as in steady state.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: June 21, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Hideaki Yokouchi, Tatsuo Nishimaki