Patents by Inventor Tatsuo Nishimaki
Tatsuo Nishimaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7218538Abstract: A power source device is provided including a boosting circuit for stepping-up an input voltage to a desired output voltage, a starter circuit for starting the boosting circuit in a starting period thereof, and a drive circuit for driving the boosting circuit as a substitute for the starter circuit after the output voltage of the boosting circuit becomes equal to or greater than a predetermined level. The starter circuit comprises a starter signal generation circuit for generating a starter signal which on/off controls a MOS transistor used for stepping-up in the boosting circuit, and a determining/controlling circuit which detects whether or not a monitor voltage in the boosting circuit is equal to or greater than a predetermined level while the MOS transistor is in the on-state, and inhibits outputting if the starter signal if the monitor voltage is equal to or greater than the predetermined level.Type: GrantFiled: November 19, 2004Date of Patent: May 15, 2007Assignee: Seiko Epson CorporationInventor: Tatsuo Nishimaki
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Patent number: 6998824Abstract: A power supply circuit includes a DC—DC conversion circuit including a high side transistor and a low side transistor connected in series between a power supply voltage and a reference potential and producing a voltage as PWM controlled output which is obtained by turning “on” and “off” each of the transistors with each PWM signal. The power supply circuit also includes a PWM circuit and output driver that detects a level of an intermediate node potential at a junction point of the high side transistor and the low side transistor after turning “off” the high side transistor, and turning “on” the low side transistor when the intermediate node potential becomes below or equal to a predetermined potential.Type: GrantFiled: July 18, 2003Date of Patent: February 14, 2006Assignee: Seiko Epson CorporationInventor: Tatsuo Nishimaki
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Patent number: 6927986Abstract: A PWM circuit is provided that is capable of PWM control with duties in a range of 0-100%, and that is also capable of high-speed responses.Type: GrantFiled: March 26, 2003Date of Patent: August 9, 2005Assignee: Seiko Epson CorporationInventor: Tatsuo Nishimaki
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Publication number: 20050168163Abstract: A power source device is provided including a boosting circuit for stepping-up an input voltage to a desired output voltage, a starter circuit for starting the boosting circuit in a starting period thereof, and a drive circuit for driving the boosting circuit as a substitute for the starter circuit after the output voltage of the boosting circuit becomes equal to or greater than a predetermined level. The starter circuit comprises a starter signal generation circuit for generating a starter signal which on/off controls a MOS transistor used for stepping-up in the boosting circuit, and a determining/controlling circuit which detects whether or not a monitor voltage in the boosting circuit is equal to or greater than a predetermined level while the MOS transistor is in the on-state, and inhibits outputting if the starter signal if the monitor voltage is equal to or greater than the predetermined level.Type: ApplicationFiled: November 19, 2004Publication date: August 4, 2005Inventor: Tatsuo Nishimaki
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Patent number: 6870354Abstract: A power source circuit includes a CMOS inversion circuit including a P-channel transistor and an N-channel transistor connected in series between a power source voltage and a reference potential, the transistors being alternately turned “on” or “off” by a PWM signal input to a gate of each transistor with an “on” period of the transistors being controlled, and being capable of outputting a D.C. voltage to a load via a stabilized capacitance. The circuit also includes a detection circuit outputting a detection signal showing a state where an intermediate node potential at a connection point of the P-channel transistor and the N-channel transistor surpasses the reference potential after undershooting to a level lower than the reference potential when the N-channel transistor is turned “on” during the “off” period of the P-channel transistor. An error amplifier is provided that obtains an error signal by comparing an output from the CMOS inversion circuit with a predetermined reference voltage value.Type: GrantFiled: July 18, 2003Date of Patent: March 22, 2005Assignee: Seiko Epson CorporationInventor: Tatsuo Nishimaki
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Publication number: 20040104714Abstract: A power source circuit includes a CMOS inversion circuit including a P-channel transistor and an N-channel transistor connected in series between a power source voltage and a reference potential, the transistors being alternately turned “on” or “off” by a PWM signal input to a gate of each transistor with an “on” period of the transistors being controlled, and being capable of outputting a D.C. voltage to a load via a stabilized capacitance. The circuit also includes a detection circuit outputting a detection signal showing a state where an intermediate node potential at a connection point of the P-channel transistor and the N-channel transistor surpasses the reference potential after undershooting to a level lower than the reference potential when the N-channel transistor is turned “on” during the “off” period of the P-channel transistor.Type: ApplicationFiled: July 18, 2003Publication date: June 3, 2004Applicant: SEIKO EPSON CORPORATIONInventor: Tatsuo Nishimaki
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Publication number: 20040080303Abstract: A power supply circuit includes a DC-DC conversion circuit including a high side transistor and a low side transistor connected in series between a power supply voltage and a reference potential and producing a voltage as PWM controlled output which is obtained by turning “on” and “off” each of the transistors with each PWM signal. The power supply circuit also includes a PWM circuit and output driver that detects a level of an intermediate node potential at a junction point of the high side transistor and the low side transistor after turning “off” the high side transistor, and turning “on” the low side transistor when the intermediate node potential becomes below or equal to a predetermined potential.Type: ApplicationFiled: July 18, 2003Publication date: April 29, 2004Applicant: SEIKO EPSON CORPORATIONInventor: Tatsuo Nishimaki
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Publication number: 20030214272Abstract: A PWM circuit is provided that is capable of PWM control with duties in a range of 0-100%, and that is also capable of high-speed responses.Type: ApplicationFiled: March 26, 2003Publication date: November 20, 2003Applicant: SEIKO EPSON CORPORATIONInventor: Tatsuo Nishimaki
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Publication number: 20020050936Abstract: A self-powered USB machine. A power control switch 23 is installed in a main power circuit 21 of the USB machine. By detecting whether a voltage occurs at a +5V power terminal of a USB port, the power control switch 23 is turned on or off. A pull-up resistor 17 is connected to a switch 18 in series. And, the pull-up switch 18 is turned on or off after the power control switch 23 is turned on or off. Thereby, the power consumption is reduced.Type: ApplicationFiled: September 24, 2001Publication date: May 2, 2002Inventors: Tetsuya Kato, Tatsuo Nishimaki, Kazuhiro Sendo
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Patent number: 5384732Abstract: A semiconductor device in which not only mask options of a mask ROM can be provided in the form of a PROM but the chip size can be reduced, and an electronic appliance using the same. The semiconductor device comprises a nonvolatile storage device (12) writable electrically, and switching circuits (18, 20) controlled on the basis of data stored in the nonvolatile storage device to perform wiring switching. Because wirings A, B1 and B2 are switched on the basis of data stored in the nonvolatile storage device, for example, optional functions of a one-chip micro computer can be provided in the form of a PROM by using the wiring switching.Type: GrantFiled: June 24, 1993Date of Patent: January 24, 1995Assignee: Seiko Epson CorporationInventor: Tatsuo Nishimaki
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Patent number: 5323171Abstract: A power source circuit consisting of a combination of a constant-voltage circuit (1) and a voltage raising/lowering circuit (2) which produces a plurality of output voltages by raising or lowering the output of the constant-voltage circuit. When a change in the power source voltage or the presence or absence of a heavy load is detected that information is supplied as a control mode signal to both the circuit (1) and circuit (2). For instance, when the power source voltage is reduced or when a heavy load is driven, the output voltage of the circuit (1) lowered and instead the rate of change in the output voltage of the circuit (2) is adjusted so that the output voltage may eventually become the same as in steady state.Type: GrantFiled: September 10, 1993Date of Patent: June 21, 1994Assignee: Seiko Epson CorporationInventors: Hideaki Yokouchi, Tatsuo Nishimaki