Patents by Inventor Tatsuo Nishino
Tatsuo Nishino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107226Abstract: An image pickup apparatus capable of efficiently retrieving a subject generating a specific sound from an image is provided. The image pickup apparatus includes an image pickup circuit, a CPU, and a memory that stores a program that, when executed by the CPU, causes the image pickup apparatus to function as: detecting a specific sound from a sound acquired by a sound acquisition unit during moving image capturing, judging a direction in which the specific sound comes toward the image pickup apparatus and acquiring information about a sound direction indicating the direction of the specific sound judged, judging a direction in which the image pickup apparatus is facing and acquiring information about an image capturing direction indicating the direction of the image pickup apparatus judged, and performing control to store attribute information, a moving image acquired by the image pickup circuit, and the sound in a storage unit.Type: ApplicationFiled: September 20, 2023Publication date: March 28, 2024Inventors: Yudai ITOI, Shogo FUJIWARA, Kenichiro SASAI, Tatsuo NISHINO
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Publication number: 20240107151Abstract: An image pickup apparatus capable of easily retrieving desired-state image and sound portions through attribute information is provided. The image pickup apparatus includes an image pickup circuit, a CPU, and a memory that stores a program that, when executed by the CPU, causes the image pickup apparatus to function as the following units a sound acquisition unit that acquires a sound, a sound recognition unit that recognizes a sound acquired during moving image capturing and detects a specific sound from the sound, an image recognition unit that recognizes a moving image acquired during the moving image capturing and detects a subject from the moving image, and a control unit that calculates an evaluation result by using a score weighted in response to a sound recognition result and an image recognition result and adds the evaluation result to the moving image and the sound as attribute information.Type: ApplicationFiled: September 20, 2023Publication date: March 28, 2024Inventors: Kenichiro SASAI, Shogo FUJIWARA, Tatsuo NISHINO, Yudai ITOI
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Publication number: 20230308740Abstract: An image pickup apparatus includes an image sensor configured to perform imaging, and a control unit configured to execute pre-capture imaging that causes the image sensor to repeatedly perform imaging when receiving a first imaging instruction, and to start post-capture imaging that causes the image sensor to repeatedly perform imaging, in a case where a main object to be focused is moving when receiving a second imaging instruction during execution of the pre-capture imaging. The control unit ends the post-capture imaging in a case where the main object stops moving or an elapsed time period from when the post-capture imaging is started is equal to or longer than a predetermined time period, and stores images that satisfy a predetermined condition among a plurality of images acquired by the pre-capture imaging and the post-capture imaging.Type: ApplicationFiled: March 9, 2023Publication date: September 28, 2023Inventor: TATSUO NISHINO
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Publication number: 20230147156Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.Type: ApplicationFiled: November 9, 2022Publication date: May 11, 2023Applicant: Renesas Electronics CorporationInventors: Pratama FAJARMEGA, Tatsuo NISHINO, Takehiro SHIMIZU
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Publication number: 20220406936Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.Type: ApplicationFiled: August 29, 2022Publication date: December 22, 2022Inventors: Kazuya UEJIMA, Michio ONDA, Takashi HASE, Tatsuo NISHINO, Shiro KAMOHARA
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Patent number: 10856427Abstract: An electronic apparatus which reduces radiation noise. A housing member mounted on a circuit board fixed to a casing houses a recording medium. A metal sheet member is electrically connected to the circuit board. The housing member has a recording medium connecting clock terminal that is connected to the recording medium housed in the housing member, and a board connecting clock terminal that is connected to the circuit board. The metal sheet member has a flat portion that faces the housing member across a predetermined space, and as seen in a direction perpendicular to a flat surface of the flat portion, an area of the flat portion which faces the board connecting clock terminal is opened.Type: GrantFiled: December 9, 2019Date of Patent: December 1, 2020Assignee: CANON KABUSHIKI KAISHAInventors: Tatsuo Nishino, Noriyuki Takei
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Publication number: 20200313000Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.Type: ApplicationFiled: November 14, 2017Publication date: October 1, 2020Inventors: Kazuya UEJIMA, Shiro KAMOHARA, Michio ONDA, Takashi HASE, Tatsuo NISHINO
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Publication number: 20200214150Abstract: An electronic apparatus which reduces radiation noise. A housing member mounted on a circuit board fixed to a casing houses a recording medium. A metal sheet member is electrically connected to the circuit board. The housing member has a recording medium connecting clock terminal that is connected to the recording medium housed in the housing member, and a board connecting clock terminal that is connected to the circuit board. The metal sheet member has a flat portion that faces the housing member across a predetermined space, and as seen in a direction perpendicular to a flat surface of the flat portion, an area of the flat portion which faces the board connecting clock terminal is opened.Type: ApplicationFiled: December 9, 2019Publication date: July 2, 2020Inventors: Tatsuo Nishino, Noriyuki Takei
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Patent number: 9748155Abstract: A printed wiring board includes a power supply conductor pattern arranged on one conductor layer, one ground conductor pattern arranged on the one conductor layer, and another ground conductor pattern arranged on the another conductor layer so as to be opposed to the power supply conductor pattern. The power supply conductor pattern includes a power supply pad on which a terminal of a capacitor is to be bonded. The one ground conductor pattern includes a ground pad on which another terminal of the capacitor is to be bonded. A slit is formed in the another ground conductor pattern so as to pass through a projection portion defined by projecting the power supply pad onto the another ground conductor pattern and divide a projection portion defined by projecting the power supply conductor pattern onto the another ground conductor pattern.Type: GrantFiled: July 9, 2014Date of Patent: August 29, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Tatsuo Nishino, Kiyoshi Sekiguchi
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Publication number: 20160133532Abstract: A printed wiring board includes a power supply conductor pattern arranged on one conductor layer, one ground conductor pattern arranged on the one conductor layer, and another ground conductor pattern arranged on the another conductor layer so as to be opposed to the power supply conductor pattern. The power supply conductor pattern includes a power supply pad on which a terminal of a capacitor is to be bonded. The one ground conductor pattern includes a ground pad on which another terminal of the capacitor is to be bonded. A slit is formed in the another ground conductor pattern so as to pass through a projection portion defined by projecting the power supply pad onto the another ground conductor pattern and divide a projection portion defined by projecting the power supply conductor pattern onto the another ground conductor pattern.Type: ApplicationFiled: July 9, 2014Publication date: May 12, 2016Inventors: Tatsuo Nishino, Kiyoshi Sekiguchi
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Patent number: 7310717Abstract: A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data transfer control unit transfers data according to a transfer unit size selected from a plurality of transfer unit sizes. If the address register contains an odd address as an initial value, the data transfer control unit transfers data according to a different transfer unit size that is smaller than the selected transfer unit size. If the data transfer control unit determines that a remaining quantity of data to be transferred is smaller than the selected transfer unit size, the selected transfer unit size is switched to a smaller transfer unit size selected from the plurality of transfer unit sizes.Type: GrantFiled: June 4, 2003Date of Patent: December 18, 2007Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc., Hitachi Engineering Co., Ltd.Inventors: Tatsuo Nishino, Toru Ichien, Gou Teshima, Hiromichi Ishikura, Jyunji Ishikawa
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Patent number: 7038555Abstract: In a printed wiring board in which wiring patterns for interconnecting a plurality of integrated circuits (ICs) operating with synchronizing signals, in order to make signal transmission times between a plurality of IC's the same, consecutively formed pairs of an inductance pattern and a capacitive pattern, are constructed at each of wiring patterns for interconnecting a plurality of IC's. By changing the shapes of the inductance pattern and the capacitive pattern, it is possible to adjust signal propagation velocities and signal transmission times.Type: GrantFiled: March 31, 2005Date of Patent: May 2, 2006Assignee: Canon Kabushiki KaishaInventors: Toru Otaki, Tatsuo Nishino
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Patent number: 6940362Abstract: In a printed wiring board in which wiring patterns for interconnecting a plurality of integrated circuits (ICs) operating with synchronizing signals, in order to make signal transmission times between a plurality of IC's the same, consecutively formed pairs of an inductance pattern and a capacitive pattern, are constructed at each of wiring patterns for interconnecting a plurality of IC's. By changing the shapes of the inductance pattern and the capacitive pattern, it is possible to adjust signal propagation velocities and signal transmission times.Type: GrantFiled: June 4, 2003Date of Patent: September 6, 2005Assignee: Canon Kabushiki KaishaInventors: Toru Otaki, Tatsuo Nishino
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Publication number: 20050168956Abstract: In a printed wiring board in which wiring patterns for interconnecting a plurality of integrated circuits (ICs) operating with synchronizing signals, in order to make signal transmission times between a plurality of IC's the same, consecutively formed pairs of an inductance pattern and a capacitive pattern, are constructed at each of wiring patterns for interconnecting a plurality of IC's. By changing the shapes of the inductance pattern and the capacitive pattern, it is possible to adjust signal propagation velocities and signal transmission times.Type: ApplicationFiled: March 31, 2005Publication date: August 4, 2005Applicant: Canon Kabushiki KaishaInventors: Toru Otaki, Tatsuo Nishino
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Publication number: 20040068590Abstract: In this data processor, the semiconductor chip comprises a central processing unit, an interface controller, and a bus controller. The interface controller further includes an interface control unit, a FIFO unit, and a transfer control unit. The interface control unit outputs the data of the FIFO unit to the external side of the semiconductor chip and inputs the data inputted from the external side of the semiconductor chip to the FIFO unit. The transfer control unit performs the control to transfer the data stored in the FIFO unit by designating the transfer destination address and the control to input the data to the FIFO unit by designating the transfer source address. The control by the data transfer control device is not included in the transfer control by the transfer control device. Accordingly, the time required for the data transfer between the on-chip interface controller and the external side can be curtailed.Type: ApplicationFiled: September 22, 2003Publication date: April 8, 2004Applicants: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc., Hitachi Device Engineering Co., Ltd.Inventors: Tatsuo Nishino, Mamoru Wakabayashi, Toru Ichien
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Publication number: 20030236941Abstract: The efficiency of block data transfer can be increased without little increasing physical circuit scales. Since a data transfer control device uses a random access memory accessible by a central processing unit as a buffer area for temporarily storing read data in dual address transfer, it does not need to have a dedicated FIFO buffer and the like in itself. Since a buffer area allocated to the random access memory or its size is programmable by the central processing unit, capacity necessary to the system may be allocated to the buffer to avoid conflict with a work area by the central processing unit.Type: ApplicationFiled: June 4, 2003Publication date: December 25, 2003Applicants: Hitachi, Ltd., Renesas Northern Japan Semiconductor, Inc., Hitachi Engineering Co., Ltd.Inventors: Tatsuo Nishino, Toru Ichien, Gou Teshima, Hiromichi Ishikura, Jyunji Ishikawa
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Publication number: 20030231473Abstract: In a printed wiring board in which wiring patterns for interconnecting a plurality of integrated circuits (ICs) operating with synchronizing signals, in order to make signal transmission times between a plurality of IC's the same, consecutively formed pairs of an inductance pattern and a capacitive pattern, are constructed at each of wiring patterns for interconnecting a plurality of IC's. By changing the shapes of the inductance pattern and the capacitive pattern, it is possible to adjust signal propagation velocities and signal transmission times.Type: ApplicationFiled: June 4, 2003Publication date: December 18, 2003Applicant: Canon Kabushiki KaishaInventors: Toru Otaki, Tatsuo Nishino
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Patent number: 6652320Abstract: A shielded cable with a connector, in which the connector is connected to an end portion of the shielded cable formed by covering a plurality of cores with a shielding member, comprises an electrode portion provided with a plurality of electrodes connected to the cores, a conductive inner housing having a fitting portion for fitting to a connector which is to be fitted to the connector, and having the electrode portion therein, and a conductive outer housing which is used in combination with the inner housing and contains cores exposed from the shielded cable, wherein the outer housing is electrically connected to the shielding member, and the outer housing is electrically connected to the inner housing through a conductive connecting portion electrically connected to the fitting portion of the inner housing.Type: GrantFiled: December 13, 2002Date of Patent: November 25, 2003Assignee: Canon Kabushiki KaishaInventors: Hideho Inagawa, Makoto Takayama, Toru Osaka, Tatsuo Nishino
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Publication number: 20030104728Abstract: A shielded cable with a connector, in which the connector is connected to an end portion of the shielded cable formed by covering a plurality of cores with a shielding member, comprises an electrode portion provided with a plurality of electrodes connected to the cores, a conductive inner housing having a fitting portion for fitting to a connector which is to be fitted to the connector, and having the electrode portion therein, and a conductive outer housing which is used in combination with the inner housing and contains cores exposed from the shielded cable, wherein the outer housing is electrically connected to the shielding member, and the outer housing is electrically connected to the inner housing through a conductive connecting portion electrically connected to the fitting portion of the inner housing.Type: ApplicationFiled: December 13, 2002Publication date: June 5, 2003Applicant: CANON KABUSHIKI KAISHAInventors: Hideho Inagawa, Makoto Takayama, Toru Osaka, Tatsuo Nishino
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Publication number: 20020025722Abstract: A shielded cable with a connector, in which the connector is connected to an end portion of the shielded cable formed by covering a plurality of cores with a shielding member, comprises an electrode portion provided with a plurality of electrodes connected to the cores, a conductive inner housing having a fitting portion for fitting to a connector which is to be fitted to the connector, and having the electrode portion therein, and a conductive outer housing which is used in combination with the inner housing and contains cores exposed from the shielded cable, wherein the outer housing is electrically connected to the shielding member, and the outer housing is electrically connected to the inner housing through a conductive connecting portion electrically connected to the fitting portion of the inner housing.Type: ApplicationFiled: August 1, 2001Publication date: February 28, 2002Inventors: Hideho Inagawa, Makoto Takayama, Toru Osaka, Tatsuo Nishino