Patents by Inventor Tatsuo OGURA

Tatsuo OGURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210272640
    Abstract: A semiconductor memory device includes a plurality of conductive layers, a semiconductor layer opposed to the plurality of conductive layers, and an electric charge accumulation portion disposed between the semiconductor layer and the plurality of conductive layers. The electric charge accumulation portion includes a plurality of first electric charge accumulation portions opposed to the plurality of conductive layers, and a plurality of second electric charge accumulation portions disposed in positions different from the plurality of first electric charge accumulation portions. A distance between the first electric charge accumulation portion and the semiconductor layer is smaller than a distance between the second electric charge accumulation portion and the semiconductor layer. A distance between the second electric charge accumulation portion and the conductive layers is smaller than a distance between the first electric charge accumulation portion and the conductive layers.
    Type: Application
    Filed: September 8, 2020
    Publication date: September 2, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Tatsuo OGURA, Takashi KURUSU, Muneyuki TSUDA, Hiroshi TAKEDA, Nayuta KARIYA
  • Patent number: 10839911
    Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuo Ogura, Hideto Horii
  • Publication number: 20200090755
    Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.
    Type: Application
    Filed: February 25, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuo OGURA, Hideto HORII