Patents by Inventor Tatsuo Ohhashi

Tatsuo Ohhashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6876210
    Abstract: A method of analyzing electromagnetic interference in which an amount of electromagnetic interference from an LSI is analyzed, wherein the method includes: an equivalent power source current information calculating step of calculating information of an equivalent power source current flowing in a power source current, from circuit information of the LSI chip; an estimating step of considering at least one of power source information of a power source for supplying a current to the LSI chip, package information of a package for the semiconductor chip, and measurement system information of a measurement system for measuring characteristics of the semiconductor chip, as analysis control information, and of estimating total information in which the analysis control information is reflected in the circuit information, as an equivalent circuit; and a total information analyzing step of performing analysis in accordance with the total information which is estimated in the estimating step.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: April 5, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Shimazaki, Shouzou Hirano, Tatsuo Ohhashi, Takashi Mizokawa, Hiroyuki Tsujikawa
  • Patent number: 6782347
    Abstract: A method for optimizing electromagnetic interference (EMI) comprising: an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation; a step of selecting an instance with a large quantity of noise in said EMI analyzing step; and a step of adjusting a driving capability of said instance so that it is lowered to an extent that a delay does not occur in a signal timing of said instance selected. In order to optimize the analyzed EMI, the portion for which optimizing is required is extracted, and such a measure as increasing the area where the decoupling capacitance is created is implemented for this portion in a necessary degree. Further, by changing the aspect ratio of the block, changing the block position or changing the cell line, the decoupling capacitance can be easily created at the most efficient inserting position.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: August 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shouzou Hirano, Takashi Mizokawa, Tatsuo Ohhashi, Kenji Shimazaki, Hiroyuki Tsujikawa
  • Publication number: 20020075018
    Abstract: A method of analyzing electromagnetic interference in which an amount of electromagnetic interference from an LSI is analyzed, wherein the method includes: an equivalent power source current information calculating step of calculating information of an equivalent power source current flowing in a power source current, from circuit information of the LSI chip; an estimating step of considering at least one of power source information of a power source for supplying a current to the LSI chip, package information of a package for the semiconductor chip, and measurement system information of a measurement system for measuring characteristics of the semiconductor chip, as analysis control information, and of estimating total information in which the analysis control information is reflected in the circuit information, as an equivalent circuit; and a total information analyzing step of performing analysis in accordance with the total information which is estimated in the estimating step.
    Type: Application
    Filed: November 27, 2001
    Publication date: June 20, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Shimazaki, Shouzou Hirano, Tatsuo Ohhashi, Takashi Mizokawa, Hiroyuki Tsujikawa
  • Publication number: 20020065643
    Abstract: A method for optimizing electromagnetic interference (EMI) comprising: an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation; a step of selecting an instance with a large quantity of noise in said EMI analyzing step; and a step of adjusting a driving capability of said instance so that it is lowered to an extent that a delay does not occur in a signal timing of said instance selected. In order to optimize the analyzed EMI, the portion for which optimizing is required is extracted, and such a measure as increasing the area where the decoupling capacitance is created is implemented for this portion in a necessary degree. Further, by changing the aspect ratio of the block, changing the block position or changing the cell line, the decoupling capacitance can be easily created at the most efficient inserting position.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 30, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shouzou Hirano, Takashi Mizokawa, Tatsuo Ohhashi, Kenji Shimazaki, Hiroyuki Tsujikawa
  • Patent number: 5737956
    Abstract: A pressure-receiving plate for a friction device includes an annular portion and pawls formed integrally on the inner or outer periphery of the annular portion. The annular portion has one side provided with a friction surface which contacts a friction disk engaged with one of a driving member and a driven member, and another side provided with reduced-thickness portions formed by applying crushing work that takes hardness and surface roughness of the friction surface into consideration. The pawls are engaged with the other of the driving member and driven member.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: April 14, 1998
    Assignees: Aisin Seiki Kabushiki Kaisha, Marujun Seiki Ind. Co., Ltd.
    Inventors: Shigeo Takahashi, Yoshitaka Soga, Tatsuo Ohhashi, Hirotaka Ito
  • Patent number: 5617941
    Abstract: A pressure-receiving plate for a friction device includes an annular portion and pawls formed integrally on the inner or outer periphery of the annular portion. The annular portion has one side provided with a friction surface which contacts a friction disk engaged with one of a driving member and a driven member, and another side provided with reduced-thickness portions formed by applying crushing work that takes hardness and surface roughness of the friction surface into consideration. The pawls are engaged with the other of the driving member and driven member.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: April 8, 1997
    Assignees: Aisin Seiki Kabushiki Kaisha, Marujun Seiki Ind. Co., Ltd.
    Inventors: Shigeo Takahashi, Yoshitaka Soga, Tatsuo Ohhashi, Hirotaka Ito