Abstract: A method includes a step of applying an aqueous 2-package type first colored paint to form an uncured first colored coating film; a step of applying an aqueous 1-package type second colored paint to form an uncured second colored coating film; a step of applying a solvent-based 2-package type clear paint to form an uncured clear coating film; and a step of heating the uncured first colored coating film, the uncured second colored coating film and the uncured clear coating film to 75 to 100° C. to simultaneously cure these films. The solvent-based 2-package type clear paint contains a hydroxyl group-containing acrylic resin and a polyisocyanate compound in a ratio of 1.5 to 2.0 equivalents of isocyanate groups in the polyisocyanate compound relative to 1 equivalent of hydroxyl groups in the hydroxyl group-containing acrylic resin.

Abstract: Methods and apparatus provide for acquiring position information about a head-mounted display; performing information processing using the position information about the head-mounted display; generating and outputting data of an image to be displayed as a result of the information processing; and generating and outputting data of an image of a user guide indicating position information about a user in a real space using the position information about the head-mounted display, where the image of the user guide represents a state of the real space in which the user is physically located, as viewed obliquely.

Abstract: There is provided an information processing device including a photographed-image acquisition section that acquires a photographed image taken by a camera mounted on a head-mount display, and a photographing parameter that is adjusted according to a brightness with use of the camera, and a play area control section that detects a play area for defining a movable range of a user by analyzing the photographed image while changing an analysis condition according to an estimated brightness on the basis of the photographing parameter, and then, acquiring 3D information regarding a real object.

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: An amplitude regulation circuit which includes a maximum detection circuit which outputs a maximum signal MAX that is distorted to some extent during and around a time when a highest-level signal switches between signals V1, V2, and V3. The amplitude regulation circuit also includes a minimum detection circuit which outputs a minimum signal MIN that is distorted to some extent during and around a time when a lowest-level signal switches between signals V1, V2, and V3. Such distortions reduce variations in amplitude detection signal AMP that represents a difference between MAX and MIN. The amplitude regulation circuit amplifies rotor position signals H1 to H3 based on amplitude detection signal AMP according to AGC, thereby maintaining amplitudes of signals V1 to V3 constant while maintaining sinusoidal waveforms.

Abstract: An amplitude regulation circuit which includes a maximum detection circuit which outputs a maximum signal MAX that is distorted to some extent during and around a time when a highest-level signal switches between signals V1, V2, and V3. The amplitude regulation circuit also includes a minimum detection circuit which outputs a minimum signal MIN that is distorted to some extent during and around a time when a lowest-level signal switches between signals V1, V2, and V3. Such distortions reduce variations in amplitude detection signal AMP that represents a difference between MAX and MIN. The amplitude regulation circuit amplifies rotor position signals H1 to H3 based on amplitude detection signal AMP according to AGC, thereby maintaining amplitudes of signals V1 to V3 constant while maintaining sinusoidal waveforms.

Abstract: An amplitude regulation circuit which includes a maximum detection circuit which outputs a maximum signal MAX that is distorted to some extent during and around a time when a highest-level signal switches between signals V1, V2, and V3. The amplitude regulation circuit also includes a minimum detection circuit which outputs a minimum signal MIN that is distorted to some extent during and around a time when a lowest-level signal switches between signals V1, V2, and V3. Such distortions reduce variations in amplitude detection signal AMP that represents a difference between MAX and MIN. The amplitude regulation circuit amplifies rotor position signals H1 to H3 based on amplitude detection signal AMP according to AGC, thereby maintaining amplitudes of signals V1 to V3 constant while maintaining sinusoidal waveforms.

Abstract: In an amplitude regulation circuit, a maximum detection circuit outputs maximum signal MAX that is distorted to some extent during and around a time when a highest-level signal switches between signals V1, V2, and V3. Meanwhile, a minimum detection circuit outputs minimum signal MIN that is distorted to some extent during and around a time when a lowest-level signal switches between signals V1, V2, and V3. Such distortions serve to reduce variations in amplitude detection signal AMP that represents a difference between MAX and MIN. The amplitude regulation circuit amplifies rotor position signals H1 to H3 based on amplitude detection signal AMP according to AGC, thereby keeping amplitudes of signals V1 to V3 constant while maintaining sinusoidal waveforms. A motor driving control apparatus drives a motor based on signals V1 to V3. Since this circuitry does not include a smoothing capacitor, high AGC responsiveness is achieved.

Abstract: Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: A comb filter easily implementable as a monolithic LSI without using a large-capacitance capacitor is provided. A comb-like frequency characteristic is realized by two delay circuits for delaying a signal for mutually different amounts of time and an operation circuit for deriving a sum or difference of the outputs thereof. An input select switch selectively outputs, instead of an image signal, a test signal, which is a DC signal having a predetermined amplitude, during a blanking interval of the image signal. A detector controls the gain of a variable-gain amplifier, provided for the output of either one of the delay circuits, in accordance with a difference between the output signal of the comb filter in response to the test signal and a predetermined reference signal. That is to say, the gain of the comb filter is controlled by using a stable test signal as a control signal, instead of a burst signal contained in an unstable image signal.

Abstract: In a semiconductor memory device having cylindrical capacitors, word lines and a bit line are formed on a semiconductor substrate. A cylindrical storage node is connected to a conductive layer. The cylindrical storage node is provided at its inner wall with protruded conductive conductors which protrudes in a radially inward direction of the cylindrical storage node. A surface of the cylindrical storage node is covered with a capacitor insulating film. The outer surface of the cylindrical storage node is covered with a cell plate with the capacitor insulating film therebetween.

Abstract: The semiconductor memory device includes a semiconductor substrate 1 having a conductive layer 6 formed on its main surface. Word lines 4c, 4d and a bit line 11 is formed on the semiconductor substrate. Insulating films 8, 12 are provided to cover the word lines 4c, 4d and the bit line 11. A barrier film 14 is provided on the insulating films 8, 12 for protecting the insulating films 8, 12 from etchant. A cylindrical storage node 170 is electrically connected to the conductive layer 6. The cylindrical storage node 170 includes a bottom conductive portion 17a and a sidewall conductive portion 17b. An outer surface of the storage node 170 is covered with a capacitor insulating film 112. The outer surface of the cylindrical storage node 170 is covered with a cell plate 22, with the capacitor insulating film 112 interposed therebetween.

Abstract: The semiconductor memory device includes a semiconductor substrate 1 having a conductive layer 6 formed on its main surface. Word lines 4c, 4d and a bit line 11 is formed on the semiconductor substrate. Insulating films 8, 12 are provided to cover the word lines 4c, 4d and the bit line 11. A barrier film 14 is provided on the insulating films 8, 12 for protecting the insulating films 8, 12 from etchant. A cylindrical storage node 170 is electrically connected to the conductive layer 6. The cylindrical storage node 170 includes a bottom conductive portion 17a and a sidewall conductive portion 17b. An outer surface of the storage node 170 is covered with a capacitor insulating film 112. The outer surface of the cylindrical storage node 170 is covered with a cell plate 22, with the capacitor insulating film 112 interposed therebetween.

Abstract: An apparatus for manufacturing a heat-shrinkable tube has a die formed with a center bore through which a resin tube passes and a plurality of radial holes extending from the bore to the outer periphery of the die. The die is contained in a tank filled with a cooling fluid so that the die will be immersed in the cooling fluid. The interior of the tank is kept under reduced pressure. At the inlet side of the die, a pre-cooling unit is provided which supplies a cooling fluid to the outer periphery of a resin tube which have been heated to a temperature above its softening point beforehand. The tube is expanded at least by the suction force applied thereto while passing through the die kept under reduced pressure. The cooling fluid in the tank and that supplied from the pre-cooling unit serve to reduce the friction between the tube and the inner periphery of the die, thus preventing the tube from expanding lengthwise. A jacket may be provided around the die to supply the cooling fluid.