Abstract: According to one embodiment, a wafer includes a substrate including SiC, and a first layer including SiC. The first layer is in contact with the substrate. The first layer includes Cr. The substrate does not include Cr. Or a concentration of Cr in the substrate is lower than a concentration of Cr in the first layer. A substrate length of the substrate in a second direction crossing a first direction from the substrate to the first layer is longer than a first layer length of the first layer in the second direction.

Abstract: A magnetoresistance effect element includes a magnetic recording layer which includes a ferromagnetic material, a non-magnetic layer laminated on the magnetic recording layer, and a magnetization reference layer which is laminated on the non-magnetic layer. The magnetic recording layer includes a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer in order from the non-magnetic layer. The first ferromagnetic layer and the second ferromagnetic layer are antiferromagnetically coupled to each other.

Abstract: The present invention enables to obtain an approximate position of a zero crossing point in a shorter time period. A magnetic position sensor detects, with an array in which multiple magnetic detection elements are arranged in a straight line, the zero crossing point at which the magnetic flux density from a pair of magnetic poles is zero in a plane perpendicular to the longitudinal direction of the array. The magnetic detection elements are elements whose output changes in polarity when the direction of the magnetic flux density is inverted, and detect an approximate position of the zero crossing point by reading an output of every k-th magnetic detection element of the array (where k is an integer of 2 or greater). Then, the position of the zero crossing point is detected according to outputs of at least two magnetic detection elements on both sides of the zero crossing point.

Abstract: In a linear displacement sensor, two magnets with different polarities define one pitch of a magnetic scale. kn (k is a natural number greater than or equal to 2, n is a natural number greater than or equal to 1) sensor units configured to output a plurality of signals whose period is one pitch and whose phases with respect to the pitch are different are arranged along the magnetic scale in a one-pitch segment. Periodic errors with n periods per pitch of the sensor units are canceled out by averaging the phases from the kn sensor units.

Abstract: A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate; semiconductor elements for electric power which are affixed to the surface of the front-surface electrode pattern; a partition wall which is provided on the front-surface electrode pattern so as to enclose the semiconductor elements for electric power; a first sealing resin member which is filled inside the partition wall; a second sealing resin member which covers the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall, wherein an electrode for a relay terminal is provided on a surface of the partition wall, and a wiring from inside of the partition wall to outside of the partition wall is led out via the electrode for a relay terminal.

Abstract: The present invention enables to obtain an approximate position of a zero crossing point in a shorter time period. A magnetic position sensor detects, with an array in which multiple magnetic detection elements are arranged in a straight line, the zero crossing point at which the magnetic flux density from a pair of magnetic poles is zero in a plane perpendicular to the longitudinal direction of the array. The magnetic detection elements are elements whose output changes in polarity when the direction of the magnetic flux density is inverted, and detect an approximate position of the zero crossing point by reading an output of every k-th magnetic detection element of the array (where k is an integer of 2 or greater). Then, the position of the zero crossing point is detected according to outputs of at least two magnetic detection elements on both sides of the zero crossing point.

Abstract: In a linear displacement sensor, two magnets with different polarities define one pitch of a magnetic scale. kn (k is a natural number greater than or equal to 2, n is a natural number greater than or equal to 1) sensor units configured to output a plurality of signals whose period is one pitch and whose phases with respect to the pitch are different are arranged along the magnetic scale in a one-pitch segment. Periodic errors with n periods per pitch of the sensor units are canceled out by averaging the phases from the kn sensor units.

Abstract: A semiconductor device includes: a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate and a back-surface electrode is formed on another surface; semiconductor elements affixed to the surface of the front-surface electrode pattern opposite the insulating substrate; and a sealing resin member which covers the semiconductor element and the semiconductor-element substrate, wherein at a position of the front-surface electrode pattern where the position has potential equivalent to that of the front-surface electrode pattern at a position where a semiconductor element is bonded, an insulating terminal table formed with a conductive relay terminal and an insulating member that insulates the relay terminal and the front-surface electrode pattern from each other are provided, and wiring from the semiconductor element to the outside is led out via the relay terminal.

Abstract: A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate; semiconductor elements for electric power which are affixed to the surface of the front-surface electrode pattern; a partition wall which is provided on the front-surface electrode pattern so as to enclose the semiconductor elements for electric power; a first sealing resin member which is filled inside the partition wall; a second sealing resin member which covers the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall, wherein an electrode for a relay terminal is provided on a surface of the partition wall, and a wiring from inside of the partition wall to outside of the partition wall is led out via the electrode for a relay terminal.

Abstract: A power module according to the present invention is a power module configured such that a power device chip is arranged within an outer casing and an electrode of the power device chip is connected to an external electrode that is integrated with the outer casing. The power module includes: a heat spreader fixed inside the outer casing; the power device chip solder-bonded on the heat spreader; an insulating dam formed on the heat spreader so as to surround the power device chip; and an internal main electrode having one end thereof solder-bonded to the electrode of the power device chip and the other end thereof fixed to an upper surface of the dam. The external electrode and the other end of the internal main electrode are electrically connected to each other by wire bonding.

Abstract: A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns.

Abstract: A semiconductor device includes: a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate and a back-surface electrode is formed on another surface; semiconductor elements affixed to the surface of the front-surface electrode pattern opposite the insulating substrate; and a sealing resin member which covers the semiconductor element and the semiconductor-element substrate, wherein at a position of the front-surface electrode pattern where the position has potential equivalent to that of the front-surface electrode pattern at a position where a semiconductor element is bonded, an insulating terminal table formed with a conductive relay terminal and an insulating member that insulates the relay terminal and the front-surface electrode pattern from each other are provided, and wiring from the semiconductor element to the outside is led out via the relay terminal.

Abstract: A power module according to the present invention is a power module configured such that a power device chip is arranged within an outer casing and an electrode of the power device chip is connected to an external electrode that is integrated with the outer casing. The power module includes: a heat spreader fixed inside the outer casing; the power device chip solder-bonded on the heat spreader; an insulating dam formed on the heat spreader so as to surround the power device chip; and an internal main electrode having one end thereof solder-bonded to the electrode of the power device chip and the other end thereof fixed to an upper surface of the dam. The external electrode and the other end of the internal main electrode are electrically connected to each other by wire bonding.

Abstract: A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns.

Abstract: A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns.

Abstract: A semiconductor device has a substrate, a semiconductor element, an electrode lead, and a sealing resin portion. The substrate has a main surface on which a circuit pattern is formed. The semiconductor element has first and second surfaces, and is arranged on the substrate such that the first surface faces the main surface. The electrode lead has one end joined to the circuit pattern and the other end joined by soldering to the second surface. The other end has a plurality of portions divided from each other. The sealing resin portion seals the semiconductor element and the electrode lead. Thus, there can be provided a semiconductor device that has relieved thermal stress at a joining portion of the electrode lead, and therefore is less subject to fatigue failure.

Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.

Abstract: A semiconductor device has a substrate, a semiconductor element, an electrode lead, and a sealing resin portion. The substrate has a main surface on which a circuit pattern is formed. The semiconductor element has first and second surfaces, and is arranged on the substrate such that the first surface faces the main surface. The electrode lead has one end joined to the circuit pattern and the other end joined by soldering to the second surface. The other end has a plurality of portions divided from each other. The sealing resin portion seals the semiconductor element and the electrode lead. Thus, there can be provided a semiconductor device that has relieved thermal stress at a joining portion of the electrode lead, and therefore is less subject to fatigue failure.

Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a base plate, an insulating substrate on the base plate, and a wiring patterned layer on the insulating substrate. Also, it includes at least one semiconductor chip bonded on the wiring patterned layer, the semiconductor chip having a surface electrode. A main terminal is connected via a conductive adhesive layer onto at least either one of the surface electrode and the wiring patterned layer. Also, a resin package covers the insulating substrate, the wiring patterned layer, the semiconductor chip, the conductive adhesive layer, and at least a portion of the main terminal.

Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a base plate, an insulating substrate on the base plate, and a wiring patterned layer on the insulating substrate. Also, it includes at least one semiconductor chip bonded on the wiring patterned layer, the semiconductor chip having a surface electrode. A main terminal is connected via a conductive adhesive layer onto at least either one of the surface electrode and the wiring patterned layer. Also, a resin package covers the insulating substrate, the wiring patterned layer, the semiconductor chip, the conductive adhesive layer, and at least a portion of the main terminal.