Patents by Inventor Tatsuo Otsuki
Tatsuo Otsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6924997Abstract: A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.Type: GrantFiled: September 25, 2001Date of Patent: August 2, 2005Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Zheng Chen, Vikram Joshi, Myoungho Lim, Carlos A. Paz de Araujo, Larry D. McMillan, Yoshihisa Kato, Tatsuo Otsuki, Yasuhiro Shimada
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Patent number: 6876030Abstract: A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.Type: GrantFiled: September 20, 2001Date of Patent: April 5, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Yasuhiro Shimada, Koji Arita, Tatsuo Otsuki
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Publication number: 20040047174Abstract: A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.Type: ApplicationFiled: October 9, 2003Publication date: March 11, 2004Inventors: Zheng Chen, Vikram Joshi, Myoungho Lim, Carlos A. Paz de Araujo, Larry D. McMillan, Yoshihisa Kato, Tatsuo Otsuki, Yasuhiro Shimada
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Patent number: 6653156Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.Type: GrantFiled: September 30, 2002Date of Patent: November 25, 2003Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
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Patent number: 6541806Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.Type: GrantFiled: January 14, 1999Date of Patent: April 1, 2003Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
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Publication number: 20030034548Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.Type: ApplicationFiled: September 30, 2002Publication date: February 20, 2003Applicant: Symetrix CorporationInventors: Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
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Patent number: 6469334Abstract: A ferroelectric FET having an interface insulator layer containing ZrO2. The ferroelectric FET includes a gate oxide layer, the interface insulator layer is located on the gate oxide layer, and ferroelectric layered superlattice material is located on the interface insulator layer, The interface insulator layer has a thickness of from 15 to 25 nanometers.Type: GrantFiled: March 29, 2001Date of Patent: October 22, 2002Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
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Patent number: 6447838Abstract: A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100° C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700° C. for a barrier thickness of about 1000 Å and about 800° C. for a barrier thickness of about 3000 Å. The barrier layer is 800 Å thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.Type: GrantFiled: October 16, 1995Date of Patent: September 10, 2002Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Masamichi Azuma, Eiji Fujii, Yasuhiro Uemoto, Shinichiro Hayashi, Toru Nasu, Yoshihiro Shimada, Akihiro Matsuda, Tatsuo Otsuki, Michael C. Scott, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
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Patent number: 6440754Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by carefully controlled drying, soft baking, and annealing conditions.Type: GrantFiled: April 26, 2001Date of Patent: August 27, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinichiro Hayashi, Tatsuo Otsuki
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Publication number: 20020036314Abstract: A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.Type: ApplicationFiled: September 20, 2001Publication date: March 28, 2002Inventors: Kiyoshi Uchiyama, Yasuhiro Shimada, Koji Arita, Tatsuo Otsuki
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Patent number: 6333528Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: December 25, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Publication number: 20010041372Abstract: A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1−xZrx)O2, wherein 0≦x≦1.Type: ApplicationFiled: March 29, 2001Publication date: November 15, 2001Applicant: Symetrix CorporationInventors: Koji Arita, Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
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Publication number: 20010041373Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by carefully controlled drying, soft baking, and annealing conditions.Type: ApplicationFiled: April 26, 2001Publication date: November 15, 2001Applicant: Matsushita Electronics CorporationInventors: Shinichiro Hayashi, Tatsuo Otsuki
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Patent number: 6294438Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: June 8, 2000Date of Patent: September 25, 2001Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Publication number: 20010011738Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.Type: ApplicationFiled: January 14, 1999Publication date: August 9, 2001Inventors: SHINICHIRO HAYASHI, TATSUO OTSUKI, CARLOS A. PAZ DE ARAUJO
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Patent number: 6265738Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by carefully controlled drying, soft baking, and annealing conditions.Type: GrantFiled: March 3, 1997Date of Patent: July 24, 2001Assignee: Matsushita Electronics CorporationInventors: Shinichiro Hayashi, Tatsuo Otsuki
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Patent number: 6255121Abstract: A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1-xZrx)O2, wherein 0≦x≦1.Type: GrantFiled: February 26, 1999Date of Patent: July 3, 2001Assignees: Symetrix Corporation, Matsushita Electronics CorporationInventors: Koji Arita, Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
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Patent number: 6169304Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: January 2, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 6151241Abstract: A ferroelectric field effect transistor memory cell includes a thin film varistor located between the gate electrode and the ferroelectric layer. The varistor protects the ferroelectric layer from disturb voltage pulses arising from memory read, write and sense operations. A second electrode is located between the thin film varistor and the ferroelectric layer. The thin film ferroelectric is positioned over the channel of a transistor to operate as a ferroelectric gate. For voltages at which disturb voltages are likely to occur, the thin film varistor has a resistance obeying a formula R.sub.d >10.times.1/(2.pi.fC.sub.F), where R.sub.d is resistivity of the thin film varistor, f is an operating frequency of said memory, and C.sub.F is the capacitance of the ferroelectric layer. For voltages at or near the read and write voltage of the memory, the thin film varistor has a resistance obeying a formula R.sub.d <0.1.times.1/(2.pi.fC.sub.F).Type: GrantFiled: May 19, 1999Date of Patent: November 21, 2000Assignees: Symetrix Corporation, Matsushita Electronics CorporationInventors: Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
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Patent number: RE38565Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by carefully controlled drying, soft baking, and annealing conditions.Type: GrantFiled: February 6, 2003Date of Patent: August 17, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinichiro Hayashi, Tatsuo Otsuki