Patents by Inventor Tatsuo Sakaue

Tatsuo Sakaue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4809307
    Abstract: A charge transfer device includes a charge transfer unit having a plurality of charge transfer cells for transferring a signal charge by the charge transfer cells, a first floating diffusion region adjacent to the charge transfer unit for storing the signal charge transferred by the charge transfer cells, first control switch means driven by a first reset pulse, and a first reset power source connected to the first floating diffusion region through the first control switch means. The charge transfer device further includes second control switch means driven by a second reset pulse, a second reset power source connected to the second floating diffusion region through the second control switch means, a capacitor coupling the first floating diffusion region to the second floating diffusion region, and detector means for detecting a potential change of the second floating diffusion region to output the potential change as an output signal corresponding to the signal charge.
    Type: Grant
    Filed: March 30, 1987
    Date of Patent: February 28, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Sakaue, Tatsuya Yoshie
  • Patent number: 4528684
    Abstract: A circuit for obtaining an output from a CCD type signal processing circuit should operate satisfactorily in a high frequency band covering, for instance, video signals. For this purpose, the floating gate electrode of the CCD is connected to a first potential point through first and second capacitors. The connecting point of the floating gate electrode in the series circuit is connected to a second potential level through a first control switch which is driven by a reset clock pulse, and the connecting point of the first and second capacitors is connected to a third potential level through a second control switch which is driven by a reset clock pulse, so that the output is provided at the connecting point of the capacitors.
    Type: Grant
    Filed: July 22, 1983
    Date of Patent: July 9, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tetsuya Iida, Tatsuo Sakaue
  • Patent number: 4489245
    Abstract: In an integrated circuit having an amplifier with its input terminal connected to a signal input terminal, a D.C. voltage bias circuit is provided which includes a D.C. bias voltage generator and a depletion mode MOS transistor connected at its source-drain path between the bias voltage generator and the signal input terminal and coupled at its gate electrode to either its source or its drain thus preventing breakdown of the gate insulating film of the depletion mode MOS transistor resulting from a surge voltage from the signal terminal.
    Type: Grant
    Filed: April 11, 1984
    Date of Patent: December 18, 1984
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Iida, Tatsuo Sakaue
  • Patent number: 4446567
    Abstract: A dynamic shift register circuit comprises an input terminal and an output terminal. It further comprises a first transfer gate circuit connected to the input terminal for receiving an input signal and transferring the input signal under the control of a first clock signal; an inverter circuit for inverting a level of an output signal of the first transfer gate circuit; a second transfer gate circuit connected to the inverter circuit for receiving an output signal of the inverter circuit and transferring the same under the control of a second clock signal which has a level opposite to that of the first clock signal; a signal follower circuit for producing an output signal having a level which follows a level of the output signal of the first transfer gate circuit; and a logic circuit connected to first and second power source voltages.
    Type: Grant
    Filed: February 25, 1981
    Date of Patent: May 1, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tetsuya Iida, Tatsuo Sakaue
  • Patent number: 4377794
    Abstract: A CCD comb filter includes long and short CCD delay lines connected to receive a common input signal and is arranged to combine output signals of the long and short CCD delay lines. In order to realize a CCD comb filter very close to an optimum comb filter the product of the number of stages of the long CCD delay line and the transfer inefficiency of each stage thereof is set substantially equal to the product of the number of stages of the short CCD delay line and the transfer inefficiency of each stage thereof. In order that the transfer inefficiency of the short CCD delay line may be made greater to satisfy the above-mentioned requirement, transfer electrodes of the short CCD delay line are designed such that their length as viewed in charge transfer direction is made larger than the length of transfer electrodes of the long CCD delay line.
    Type: Grant
    Filed: March 5, 1981
    Date of Patent: March 22, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tatsuo Sakaue, Chikara Sato
  • Patent number: 4342004
    Abstract: The comparator circuit of the invention is provided with a bias voltage generating section which produces a bias voltage corresponded to an output voltage of a differential amplifier section. The bias voltage of the bias voltage generating section is applied to the load elements of a linear amplifier section, which have the same characteristic respectively.On the other hand the output voltage from the differential amplifier section is converted into DC operating point voltage of the linear amplifier section, which is applied to the drive elements of which characteristics are same each other.
    Type: Grant
    Filed: May 12, 1980
    Date of Patent: July 27, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tetsuya Iida, Tatsuo Sakaue
  • Patent number: 4322696
    Abstract: A circuit for supplying weighting voltages to multipliers of a transversal filter comprises a plurality of electronic switches associated with the multipliers for switching magnitudes of the weighting voltages applied to the multipliers, and memory cells associated with the respective electronic switches for storing digital data to turn on or off the corresponding electronic switches. Those memory cells are sequentially addressed by address circuits to store data which define the magnitudes of the weighting voltages applied to the multipliers.
    Type: Grant
    Filed: February 5, 1980
    Date of Patent: March 30, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tatsuo Sakaue, Tetsuya Iida, Chikara Sato
  • Patent number: 4316100
    Abstract: Disclosed is a charge transfer device, like a transversal filter, having means for detecting if an amount of signal charge transferred from one stage to another falls within a dynamic range of the device. A charge transfer channel is so formed as to have first and second branched output ports. A signal charge transferred to the first output port is detected as an output signal supplied to a utilization circuit while an output voltage caused by a signal charge transferred to the second output port is compared with first and second reference voltages which correspond to first and second amounts of signal charges substantially determining upper and lower limits of the dynamic range of the device, whereby it is detected if the amount of the signal charge transferred is within the dynamic range or not. As a result of the detection when the signal charge amount is outside the dynamic range, the supply of the output signal to the utilization circuit is interrupted.
    Type: Grant
    Filed: April 23, 1980
    Date of Patent: February 16, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tatsuo Sakaue, Tetsuya Iida
  • Patent number: 4249145
    Abstract: An input-weighted charge transfer transversal filter which comprises a charge transfer device including a plurality of stages, a plurality of signal charge injectors to inject into the stages of the charge transfer device weighted signal charge packets containing an AC component and a DC component, and a sense amplifier to sense the output signal of the transversal filter from the final stage of the charge transfer device, a DC charge injector to inject a predetermined quantity of DC charge into the first stage of the charge transfer device, and charge drains respectively coupled to the stages of the charge transfer device to drain at least DC charge from stages. Due to this arrangement the quantity of DC component injected by the signal charge injectors and transferred through the charge transfer device will be reduced. This leads to an improvement in packing density and signal detecting capability of the transversal filter.
    Type: Grant
    Filed: August 3, 1979
    Date of Patent: February 3, 1981
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tatsuo Sakaue, Yasoji Suzuki, Tetsuya Iida
  • Patent number: 4162411
    Abstract: An analog signal processing apparatus of series write-in and parallel read-out type includes a charge transfer device with a plurality of stages and for transferring sampled analog signal charge packets in response to transfer pulses applied. After stoppage of transfer pulses supply, a signal charge packet is shifted to a storage region provided adjacent to a signal charge storage site at each stage. The signal charge packet is kept in the storage region until an analog input signal is rewritten into the device. A signal charge read-out device is coupled with the storage region. The amount of signal charge stored in the storage region increases with time during the charge storage period of time due to generation of dark current charge. Means for removing dark current charge is provided.
    Type: Grant
    Filed: June 3, 1977
    Date of Patent: July 24, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Tatsuo Sakaue, Mineo Iwasawa
  • Patent number: 4127874
    Abstract: A feedback type ghost killer removes a ghost signal component from a detected composite video signal including a wanted video signal and the unwanted ghost signal. The delay time and relative amplitude of the ghost signal to the wanted video signal are detected by a detector with a plurality of tapped outputs. When an output signal appears on one of tapped outputs, the tap position represents the delay time and the amplitude of the output signal indicates the relative amplitude. The composite video signal and the output signals of the detector are supplied to a transversal filter to form a pseudo-ghost signal. The tapped outputs of the detector are used to weight the video signal in the transversal filter. The pseudo-ghost signal and the video signal are subtractively combined to remove the ghost signal from the video signal.
    Type: Grant
    Filed: May 26, 1977
    Date of Patent: November 28, 1978
    Assignees: Tokyo Shibaura Electric Co., Ltd., Nippon Hoso Kyokai
    Inventors: Mineo Iwasawa, Tatsuo Sakaue, Hikaru Date, Takehiro Takamatsu
  • Patent number: 4080581
    Abstract: A charge transfer transversal filter, wherein an input signal to the filter is branched off; an electric charge is generated in a semiconductor substrate according to each branch of the input signal supplied thereto; the electric charge is so weighted as to cause the filter to have a desired frequency characteristic; an electric charge thus weighted is introduced into a potential well of one delay means of a charge transfer device to be added to the electric charge transferred to the well from the preceding delay means; and the resultant mixture of electric charges is transferred through the charge transfer device.
    Type: Grant
    Filed: April 29, 1976
    Date of Patent: March 21, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Tatsuo Sakaue, Nobuo Suzuki