Patents by Inventor Tatsuo Tonedachi
Tatsuo Tonedachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047443Abstract: According to one embodiment, a semiconductor device includes a substrate, a first element and a second element on or above a first surface of the substrate, the first element and the second element each including a first terminal, a second terminal, and a gate, a light emitter, a light receiver configured to place the first element and the second element in an ON state or an OFF state according to an emitting state of the light emitter, and a first interconnect electrically coupling the first terminal of the first element and the first terminal of the second element to each other, the first interconnect being a sheet-shaped conductor.Type: ApplicationFiled: February 24, 2023Publication date: February 8, 2024Inventors: Jia LIU, Tatsuo TONEDACHI
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Patent number: 11611009Abstract: According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.Type: GrantFiled: September 2, 2021Date of Patent: March 21, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Masahiko Hori, Tatsuo Tonedachi, Yoshinari Tamura, Mami Fujihara
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Publication number: 20230080478Abstract: A semiconductor package includes a PDA chip, a MOS chip, and a wiring plate including a first principal surface and a second principal surface, the first principal surface being provided with a first rigid plate that is non-conductive and a second rigid plate that is conductive, the PDA chip being fixed to the first rigid plate by using a non-conductive bonding agent, a lower surface terminal of the MOS chip being soldered to the second rigid plate, the second principal surface being provided with an input terminal and an output terminal, the input terminal being electrically connected to the PDA chip, the output terminal being electrically connected to the second rigid plate.Type: ApplicationFiled: February 22, 2022Publication date: March 16, 2023Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Jia LIU, Toshihiro TSUJIMURA, Masahiko HORI, Tatsuo TONEDACHI
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Publication number: 20220302337Abstract: According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.Type: ApplicationFiled: September 2, 2021Publication date: September 22, 2022Inventors: Masahiko HORI, Tatsuo TONEDACHI, Yoshinari TAMURA, Mami FUJIHARA
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Publication number: 20220285333Abstract: A photorelay of an embodiment includes a polyimide substrate having a first surface and a second surface on an opposite side of the polyimide substrate from the first surface, the polyimide substrate having a thickness equal to or more than 10 ?m and equal to or less than 120 ?m, an input terminal provided on the second surface, an output terminal provided on the second surface, a light receiving element provided on the first surface, a light emitting element provided on the light receiving element, and a MOSFET provided on the first surface.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventor: Tatsuo Tonedachi
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Patent number: 11367715Abstract: A photorelay of an embodiment includes a polyimide substrate having a first surface and a second surface on an opposite side of the polyimide substrate from the first surface, the polyimide substrate having a thickness equal to or more than 10 ?m and equal to or less than 120 ?m, an input terminal provided on the second surface, an output terminal provided on the second surface, a light receiving element provided on the first surface, a light emitting element provided on the light receiving element, and a MOSFET provided on the first surface.Type: GrantFiled: September 4, 2020Date of Patent: June 21, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Tatsuo Tonedachi
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Publication number: 20220077022Abstract: A semiconductor device includes a circuit substrate having a first metal layer on a first side, a second metal later on a second side, and an insulating layer between the first and second metal layers. A semiconductor chip is on the first side of the circuit substrate. A metal plate is on the second side. A solder layer is between the metal plate and the second metal layer. The second metal layer includes a protruding region which extends to a first thickness towards the metal plate, a first recessed region, and a second recessed region, each adjacent to the protruding region. The first recessed region extends to a second thickness that is less than the first thickness, and the second recessed region extends to a third thickness that is less than the first thickness.Type: ApplicationFiled: November 16, 2021Publication date: March 10, 2022Inventor: Tatsuo TONEDACHI
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Publication number: 20210175221Abstract: A photorelay of an embodiment includes a polyimide substrate having a first surface and a second surface on an opposite side of the polyimide substrate from the first surface, the polyimide substrate having a thickness equal to or more than 10 ?m and equal to or less than 120 ?m, an input terminal provided on the second surface, an output terminal provided on the second surface, a light receiving element provided on the first surface, a light emitting element provided on the light receiving element, and a MOSFET provided on the first surface.Type: ApplicationFiled: September 4, 2020Publication date: June 10, 2021Inventor: Tatsuo Tonedachi
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Patent number: 10861833Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.Type: GrantFiled: October 15, 2018Date of Patent: December 8, 2020Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuo Tonedachi
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Publication number: 20190080979Abstract: A semiconductor device includes a circuit substrate having a first metal layer on a first side, a second metal later on a second side, and an insulating layer between the first and second metal layers. A semiconductor chip is on the first side of the circuit substrate. A metal plate is on the second side. A solder layer is between the metal plate and the second metal layer. The second metal layer includes a protruding region which extends to a first thickness towards the metal plate, a first recessed region, and a second recessed region, each adjacent to the protruding region. The first recessed region extends to a second thickness that is less than the first thickness, and the second recessed region extends to a third thickness that is less than the first thickness.Type: ApplicationFiled: March 2, 2018Publication date: March 14, 2019Inventor: Tatsuo TONEDACHI
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Patent number: 10217690Abstract: A semiconductor module includes a substrate, first and second wirings on the substrate, a semiconductor package disposed on the first wiring and having a pair of main electrodes on top and bottom surfaces of the semiconductor package, and a third wiring extending between the top surface of the semiconductor package and the second wiring.Type: GrantFiled: August 4, 2016Date of Patent: February 26, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo Tonedachi, Eitaro Miyake, Kentaro Takao
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Publication number: 20190051636Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.Type: ApplicationFiled: October 15, 2018Publication date: February 14, 2019Inventor: Tatsuo TONEDACHI
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Patent number: 10147707Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.Type: GrantFiled: August 25, 2017Date of Patent: December 4, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuo Tonedachi
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Publication number: 20180240732Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.Type: ApplicationFiled: August 25, 2017Publication date: August 23, 2018Inventor: Tatsuo TONEDACHI
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Publication number: 20180158762Abstract: A semiconductor device includes a semiconductor chip having a first surface, a first electrode and a second electrode provided on the first surface, a wiring electrically connected to the first electrode at the first surface, a first metal layer on the first surface and directly contacting the second electrode, a thickness of the first metal layer in a direction orthogonal to the first surface being greater than a height of a topmost portion of the wiring in the first direction from the first surface, and a resin package contacting the semiconductor chip, the first metal layer, at least a portion of the wiring, and a first portion of the first surface and leaving a second portion of the first surface exposed.Type: ApplicationFiled: August 28, 2017Publication date: June 7, 2018Inventor: Tatsuo TONEDACHI
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Patent number: 9911721Abstract: A semiconductor device includes a light emitting element comprising a substrate having a first and a second surface and an outer edge connecting the first and second surfaces. A light emitting layer is on a central portion of the first surface but not on a peripheral portion between the central portion and the outer edge of the substrate. A first insulating layer is disposed on the peripheral portion of the first surface, a side surface of the light emitting layer, and a third surface of the light emitting layer that is spaced from the first surface of the substrate. A first electrode is electrically contacting the third surface of the light emitting layer. A light receiving element is provided in a propagation path of light emitted from the light emitting element.Type: GrantFiled: August 2, 2016Date of Patent: March 6, 2018Assignee: Kabushiki Kaisha ToshibaInventor: Tatsuo Tonedachi
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Publication number: 20170213812Abstract: A semiconductor device includes a light emitting element comprising a substrate having a first and a second surface and an outer edge connecting the first and second surfaces. A light emitting layer is on a central portion of the first surface but not on a peripheral portion between the central portion and the outer edge of the substrate. A first insulating layer is disposed on the peripheral portion of the first surface, a side surface of the light emitting layer, and a third surface of the light emitting layer that is spaced from the first surface of the substrate. A first electrode is electrically contacting the third surface of the light emitting layer. A light receiving element is provided in a propagation path of light emitted from the light emitting element.Type: ApplicationFiled: August 2, 2016Publication date: July 27, 2017Inventor: Tatsuo TONEDACHI
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Publication number: 20170154834Abstract: A semiconductor module includes a substrate, first and second wirings on the substrate, a semiconductor package disposed on the first wiring and having a pair of main electrodes on top and bottom surfaces of the semiconductor package, and a third wiring extending between the top surface of the semiconductor package and the second wiring.Type: ApplicationFiled: August 4, 2016Publication date: June 1, 2017Inventors: Tatsuo TONEDACHI, Eitaro MIYAKE, Kentaro TAKAO
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Publication number: 20150069593Abstract: In one embodiment, a semiconductor device includes a lead frame including a chip mounting portion and a lead portion separated from the chip mounting portion and having the same thickness as the chip mounting portion, a level of an upper face of the chip mounting portion being same as a level of an upper face of the lead portion. The device further includes a semiconductor chip mounted on the upper face of the chip mounting portion and electrically connected to the lead portion. The device further includes a molding resin which collectively seals up the lead frame and the semiconductor chip. The device further includes a metal film covering parts of rear faces of the chip mounting portion and the lead portion.Type: ApplicationFiled: March 10, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinichi Koyama, Koji Araki, Tatsuo Tonedachi, Kazumi Otani
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Patent number: 8686464Abstract: According to one embodiment, an LED module includes a substrate, an interconnect layer, a light emitting diode (LED) package, and a reflection member. The interconnect layer is provided on the substrate. The LED package is mounted on the interconnect layer. The reflection member is provided on a region in the substrate where the LED package is not mounted and has a property of reflecting light emitted from the LED package. The LED package includes a first lead frame, a second lead frame, an LED chip, and a resin body. The first lead frame and the second lead frame are arranged apart from each other on the same plane. The LED chip is provided above the first lead frame and the second lead frame, with one terminal connected to the first lead frame and one other terminal connected to the second lead frame.Type: GrantFiled: March 22, 2011Date of Patent: April 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Inoue, Kazuhisa Iwashita, Teruo Takeuchi, Gen Watari, Tetsuro Komatsu, Tatsuo Tonedachi