Abstract: Provided is a circuit for implementing the coding of a DVI (Digital Visual Interface) standard in a small size of hardware, at high speed, and with low power consumption. In a DVI coding circuit, the input of a number-of-levels comparison circuit 22 for judging which of the number of bits at a level “H” and the number of bits at a level “L” is larger in the input signal of the coding circuit is set at 7 bits. The output of a number-of-transitions decrease circuit 23 for decreasing the number of the transitions between adjacent two bits can be inverted for 4 bits on the basis of the output of the number-of-levels comparison circuit 22. A DC balance circuit 24 for keeping the direct current-wise balance of the output signal of the coding circuit includes a 4-bit register 31, a number-of-levels difference computation circuit 27, a condition decision circuit 28, a bit inversion circuit 29 and an addition circuit 30.

Abstract: A semiconductor integrated circuit including a plurality of ADCs subjected to interleave-operation in parallel, or a semiconductor integrated circuit including an imaging ADC using a plurality of circuit elements to be switched sequentially, in which even when an image signal of any specification is input, an output signal of the plurality of ADCs or the imaging ADC is averaged to reduce irregularities on a screen. The semiconductor integrated circuit includes a plurality of analog/digital converting circuits (11) operated in parallel for sequentially converting an analog image signal to a digital image signal, a multi-phase clock signal generating circuit (12) for generating multi-phase clock signals to be used for periodically operating the plurality of analog/digital converting circuits (11) in a certain order, and a control circuit (20) for controlling the multi-phase clock signal generating circuit (12) to change a period or an order of operating the plurality of analog/digital converting circuits (11).

Abstract: A semiconductor integrated circuit including a plurality of ADCs subjected to interleave-operation in parallel, or a semiconductor integrated circuit including an imaging ADC using a plurality of circuit elements to be switched sequentially, in which even when an image signal of any specification is input, an output signal of the plurality of ADCs or the imaging ADC is averaged to reduce irregularities on a screen. The semiconductor integrated circuit includes a plurality of analog/digital converting circuits (11) operated in parallel for sequentially converting an analog image signal to a digital image signal, a multi-phase clock signal generating circuit (12) for generating multi-phase clock signals to be used for periodically operating the plurality of analog/digital converting circuits (11) in a certain order, and a control circuit (20) for controlling the multi-phase clock signal generating circuit (12) to change a period or an order of operating the plurality of analog/digital converting circuits (11).

Abstract: Provided is a circuit for implementing the coding of a DVI (Digital Visual Interface) standard in a small size of hardware, at high speed, and with low power consumption. In a DVI coding circuit, the input of a number-of-levels comparison circuit 22 for judging which of the number of bits at a level “H” and the number of bits at a level “L” is larger in the input signal of the coding circuit is set at 7 bits. The output of a number-of-transitions decrease circuit 23 for decreasing the number of the transitions between adjacent two bits can be inverted for 4 bits on the basis of the output of the number-of-levels comparison circuit 22. A DC balance circuit 24 for keeping the direct current-wise balance of the output signal of the coding circuit includes a 4-bit register 31, a number-of-levels difference computation circuit 27, a condition decision circuit 28, a bit inversion circuit 29 and an addition circuit 30.