Patents by Inventor Tatsuro Gueshi

Tatsuro Gueshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6194752
    Abstract: A gate insulating layer and a first lower electrode are formed on a channel region of a silicon substrate, and an interlayer insulating film is formed on the silicon substrate so as to cover the first lower electrode and the gate insulating film. A buffer layer is formed on the interlayer insulating film, and a contact hole is formed in the interlayer insulating film and the buffer layer on the first lower electrode. A connecting layer and a second lower electrode are formed in the contact hole. A ferroelectric thin film and an upper electrode are formed in this order on the buffer layer so as to be brought into contact with the upper surface of the second lower electrode.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: February 27, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Satoru Ogasahara, Mitsuaki Harada, Hiroaki Furukawa, Takashi Goto, Tatsuro Gueshi, Yoshiyuki Ishizuka