Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

Abstract: A non-volatile semiconductor memory device including a memory cell transistor in a memory cell region (10a) and a peripheral transistor in a peripheral region (10b) on the same substrate has been disclosed. A metal silicide layer (28) may be included on a source/drain region (26) and a control gate (15) of a peripheral transistor and a source region (24) and a drain region (23) of a memory cell transistor. A cell contact hole (31) may be formed to provide an electrical connection to drain region (23) of a memory cell transistor. Cell contact hole (31) may be self-aligned. In this way, a cell area of a memory cell may be reduced and a resistance of the peripheral transistor may be reduced.

Abstract: In a process of fabrication of a semiconductor device having its gate insulation films differ from each other in film thickness, each of a semiconductor substrate and a gate insulation film has its surface prevented from being contaminated. This enables a new gate insulation film to be normally formed on the surface of the semiconductor substrate.

Abstract: A nonvolatile semiconductor memory device includes element isolation regions composed of a plurality of trenched groove parts formed in a semiconductor substrate, an oxide film formed among a plurality of the element isolation regions on the semiconductor substrate, a first floating gate formed on the oxide film, side wall parts formed on the oxide film from the side wall parts of the first floating gate to the end rim parts of the element isolation regions, a second floating gate formed at least on the first floating gate, and a control gate formed on the second floating gate through a gate insulation film.

Abstract: In a method of manufacturing a semiconductor device, a first sacrifice oxide film is formed on a substrate. Next, a second sacrifice oxide film is formed on the substrate by etching the first sacrifice oxide film to a predetermined depth in a first etching process. Herein, the second sacrifice oxide film is thinner than the first sacrifice oxide film. Subsequently, the second sacrifice oxide film is completely removed from a surface of the substrate in a second etching process so as to expose the surface of the substrate. Finally, an oxide film is formed on the exposed surface of the substrate.

Abstract: The present invention provides a novel double-layered floating gate memory transistor wherein drain and source regions are self-aligned with respect to a first floating gate layer and isolations regions that isolate the memory cell regions on which the memory transistors are formed are also self-aligned but with respect to a second floating gate layer overlying the first floating gate layer.

Abstract: A method for writing data into a memory transistor having a floating gate includes applying a first voltage to a control gate electrode of memory transistor and applying a second voltage to both the source and the drain electrodes of memory transistor, the second voltage being lower than the first voltage. Data is written to the memory transistor by electrons injected into the floating gate due to the F-N tunnel effect. EEPROM comprises a simultaneous-write control circuit for controlling X-address decoder and Y-address decoder so as to simultaneously select all of word lines and all of bit lines, and a source switching circuit for applying a potential equal to the drain potential to the source electrode. All of memory transistors undergo a simultaneous write operation without utilizing a channel current, so that the current consumption can be reduced in the writing operation. Further, the amount of time for pre-erasure writing operation can be reduced for a higher speed in operation of the EEPROM.

Abstract: An MOS transistor having an LDD structure is constructed in a first active region for a peripheral circuit in alignment with a first gate, by using as a mask a second active region for a memory cell. After forming a first interlayer insulating layer, a second gate having a floating gate and a control gate is formed in the second active region. A third insulating layer formed on the surface including the second gate is patterned to form a contact hole bounded by a sidewall of a side face of the second gate.

Abstract: A method is for fabricating a non-volatile semiconductor memory device with a two-layered gate electrode structure having a control gate electrode and a floating gate electrode. A first insulating film, a first amorphous silicon film, a first gate insulating film, a first polycrystalline silicon film, a second gate insulating film, and a second polycrystalline film are sequentially formed on a semiconductor substrate. Then, using a patterning mask, predetermined regions of the second polycrystalline silicon film, the second gate insulating film, the first polycrystalline silicon film, the first gate insulating film, and the first amorphous silicon film are sequentially and selectively removed, so that only element isolation regions are exposed. Thereafter, after the formation of a control gate electrode, etc., a drain region and a source region are formed on the first amorphous silicon film.

Abstract: A electrically erasable and programmable read only memory device has a memory cell array implemented by a plurality of floating gate type memory transistors, and each of the floating gate type memory transistors is implemented by a thin film field effect transistor with a floating gate electrode formed on a relatively thick insulating film covering a major surface of a semiconductor substrate so that the biasing conditions and crystal defects do not have any influence on the floating gate type memory transistor.

Abstract: A non-volatile semiconductor memory device is formed by a plurality of memory cell array groups arranged in a matrix form. Each of the memory cell array groups includes a transistor group. The transistor group is composed of a plurality of transistor pairs connected in series, the transistor pair being formed by a memory transistor and a first selecting transistor connected in parallel with each other. At least one second selecting transistor is connected between a bit line and the transistor group. The memory transistor is over-layered above the first selecting transistor. Such an arrangement of the non-volatile semiconductor memory device does not require an intermediate potential for selective write, so that the write can be made at a relatively low voltage, can avoid the problems of an excess write and an excess erasure, has a wide voltage margin for write/erasure, can be easily fabricated even if the first gate insulating film is thick, and has the functions of a word write and a word erasure.