Abstract: In a recording apparatus for video signals, adjacent pixels in input image signals are collected as blocks and subjected to orthogonal transformation. Then, the dc component, control data, ac components, end-of-block signal and the like in a block after orthogonal transformation are coded and the codewords are arranged in prescribed record areas. One or a plurality of record areas forms a correction area, and error correction coding is performed and recorded on the data in a correction area. When record data are reproduced and recorded again, errors are detected in the unit of the error correction area. The dc component and the like in a record area wherein an error which cannot be corrected exists are replaced by a codeword which is not used ordinarily, and a codeword for the first ac component is replaced by an end-of-block codeword.

Abstract: An apparatus serving as a digital videocassette recorder (VCR) for recording analog video and audio signals as digital signals. The apparatus serves also as a digital data storage drive. The digital VCR and the storage drive share common circuitry and a common magnetic recording medium. This reduces the cost and enhances the efficiency at which tracks are used. The apparatus has a large storage capacity. The apparatus divides input digital data into two parts and performs error correction encoding for each of these two data parts to form sync blocks. These sync blocks are recorded in an audio signal recording area and a video signal recording area, respectively, on the recording medium. Error correction codes used during reading of digital data are the same as those used during recording of video and audio signals. The same track structure and the same sync block structure are used for these two modes of operation.

Abstract: In a digital video signal recording and reproducing apparatus using bit rate reduction coding, information multiplexed to each record block is selected depending on the reproducing process applied to reproduce record blocks. When error correction is carried out and then, error concealment is applied to any record block having an error uncorrectable by the error correction, error concealment information indicating that the error concealment was carried out is multiplexed to the record block to be outputted. Also, since the continuity of bit rate reduction encoded data may be broken by concealing a part of record blocks, decoding information for controlling the decoding of bit rate reduction encoded data is multiplexed to the record block to be outputted. When an error concealment is not carried out in the bit rate reduction encoded state, an error flag indicating that an error exists is multiplexed to the record block to be outputted.

Abstract: In order to thin an input signal a second multiplexer is switched to output an output of a first adder and a third multiplexer is switched to output an output of a second adder, and a first multiplexer is alternatively switched at every line. A delay circuit memorizes the sum of the two preceding input signals, and the second adder outputs at every other line the sum of image data of a present line and the two preceding lines. To interpolate an input signal, the second multiplexer is switched to output the output of the delay circuit, the first multiplexer is alternatively switched to output either the input signal or the output of the second multiplexer, and the second multiplexer is alternatively switched to output either the output of the first adder or the output of the delay circuit. Thus, the delay circuit outputs at every other line the sum of the two preceding input signals.

Abstract: When quantizing the components transformed in each block, the transformed components in the block are classified into plural sets, and the quantizing width is determined in each classification, and when quantizing with a large quantizing width, the quantizing width of the transformed component belonging to the set of the transformed components less important visually is set larger.

Abstract: In order to reproduce highly important information easily and at high speed, such information is composed into data of fixed length and is assigned from the beginning of a block. Without increasing the recording rate, in order to record a signal so that the highly important information may be reproduced securely, a dummy sync block is inserted immediately before a data sync block which contains the highly important information for defining or explaining the content of the signal to be recorded. To maintain the error correction capability in a normal play mode, moreover, the sync block composition which is the same as in the signal to be recorded is used for the highly important information. In particular, as for such information, by assigning the information in plural sync blocks, reproduction is securely realized also in the case of a trick play mode.

Abstract: Each of a plurality of pages of video data are shuffled, each of the pages being composed of a plurality of blocks of data, using a data memory having a memory capacity of one page. The one page data memory temporarily stores data in a current page. A data address generator generates an address of the data memory so that the data in the current page are written into the data memory in a first sequence and the written data are read out from the data memory in a second sequence which is different from the first sequence to thereby shuffle the data in the current page. The data address generator generates the address such that data in a block in the current page is read from a portion of the data memory indicated by the address generated by the data address generator, and such that data in a block in a next page is written into the portion of the data memory indicated by the address generated by the data address generator.

Abstract: A coded digital video signal is obtained by dividing a digital video signal into plural pages each composed of K fields of pixel data, decomposing pixel data in each two pages into plural blocks each composed of a predetermined number of pixel data, and encoding the pixel data in each block by bit rate reduction encoding and error correction encoding. The thus obtained coded digital video signal is reproduced or transmitted and then subjected to a concealment process. The concealment process includes decoding the coded digital video signal to obtain reproduced blocks of pixel data and to detect an error block containing an error among the reproduced blocks, composing the reproduced blocks to obtain plural reproduced pages of pixel data, and concealing error pixel data contained in the error block in each two reproduced pages. Error pixel data in a first page is concealed using pixel data in a previous page, and error pixel data in a second page is concealed using pixel data in a succeeding page.

Abstract: Two, HD and SD, signals are arranged so as to be identical to each other in the recorded form on a recording medium. Reciver circuits, encoder circuits, and a recording circuit for SD signals are provided. Also, a receiver circuit, an encoder circuit, and a recording circuit for HD signals are provided. In addition, a circuit is provided for identifying whether the input signal is an SD or HD signal. Accordingly, both the HD and SD signals can be recorded using one single digital VCR while no further hardware is involved. Simultaneous recording of a plurality of SD signals and high-speed dubbing of SD signals may be executed using an HD signal processing circuit.

Abstract: A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing digital signal presented in sync blocks is disclosed. Each sync block has a fixed area for low frequency data and five subsequent sync blocks define a sharing group for sharing high frequency data. The signal processing apparatus includes an inner and outer correction circuit for correcting errors in the sync blocks. An error flag is provided to a sync block which still has an error remaining after the processing in the correction circuit. A memory is provided for storing errorless sync blocks of one frame. A substitution switch is provided for passing the errorless sync blocks, but substituting a sync block stored in the memory for a sync block still having some errors. Five sync blocks produced from the substitution switch are held in a delay. When no substitute sync block is detected in the five sync blocks in the delay, the data in the five sync blocks are decoded by a bit rate reduction decoder.

Abstract: An encoding and decoding apparatus for a video signal and a high-definition television signal is disclosed. For the picture A having the horizontal to vertical screen frame ratio of 4:3, the picture B having the horizontal to vertical screen frame ratio of 16:9 and the picture C having the horizontal to vertical screen frame ratio of 16:9 and having a larger number of vertical pixels than that of the picture A and picture B, the apparatus limits the band of the picture C to obtain the picture D having the same numbers of horizontal and vertical pixels respectively as those of the picture B, and high-efficiency encodes the picture A, picture B or picture D in the same method. The apparatus obtains the additional picture E which is a difference between the picture D and the picture C, or a difference between the picture D' which is a result of decoding a signal that has been obtained by high-efficiency encoding the picture D and the picture C, and then high-efficiency encodes the additional picture E obtained.

Abstract: Disclosed are a video signal recording apparatus for dividing digital video signal into blocks, transforming orthogonally, quantizing, coding in a variable length, and recording always in identical data quantity in a unit of specific number of blocks, and a video signal reproducing apparatus for decoding the recorded signal in variable length, quantizing inversely, transforming inversely and orthogonally, and reproducing the original digital video signal. The coding data in the specific number of blocks in the identical data quantity is divided in two code rows, the individual low frequency components are assigned to separate sync blocks, and high frequency components are also assigned to separate sync blocks, and recorded. When reproducing, if the sync block of high frequency components is wrong, it is possible to decode only with low frequency components, and the screen is reproduced at high fidelity to the reproducing speed at the time of high speed reproducing.

Abstract: In an apparatus for executing an algorithm for realizing an orthogonal transform operation such as the 8 points fast cosine transform, by operating on successive sets of data values of a digital signal such as a digital video signal in such applications as high efficiency coding of a digital video signal, a plurality of multiplication operations that are executed during processing of each set of data values are executed sequentially by time division multiplex operation of a single multiplier (32) which is capable of executing a multiplication operation within one sample period of the digital signal, with input and output data values being transferred by selector units (11, 33, 41) between the multiplier and other sections of the apparatus at appropriate times during processing of each set of the input digital signal values. The scale of hardware required for the apparatus is thereby reduced by comparison with an apparatus which employs a plurality of separate multipliers.

Abstract: In a video signal digital magnetic recording and/or reproducing apparatus, an input image data array is rearranged into a different data array appropriate for data compression and then subjected to a data compression by variable length coding. The resulting data are rearranged after the data compression and then recorded sequentially onto a video track of a magnetic tape in the same order as that in the frame. In a high-speed playback mode, only the lower frequency component data is decoded every sync block, so that the data reproduced from one video track adjoin each other in the playback picture on the screen.

Abstract: In the recording apparatus and reproducing apparatus employing variable length coding, a formatting which prevents propagation of error due to transmission route error is realized. The input quantized value is coded in variable length and recorded in a first memory. The variable length code words recorded in the first memory are read out and formatted, and recorded into a second memory. In reproduction, the quantized value is decoded in the reverse sequence. By executing variable length coding and formatting in a pipeline operation by using two memories, high speed input signals such as moving picture signals can be formatted. Components of the recording apparatus and reproducing apparatus can be shared, and the circuit scale may be effectively reduced.

Abstract: A data round-off device receives a digital input signal of m-bit form (m is an integer) which has arithmetically been processed by addition, subtraction, multiplication, and division by an orthogonal transformer or predictive encoder is summed, if it is positive, with a value of 2.sup.(n-1) -1 (n is a natural number smaller than m) and if negative, with a value of 2.sup.(n-1) and the higher (m-n) bits of a resultant sum signal are delivered as the output of the data round-off device. Preferably, it is used for control of the number of bits if there is a difference in the number of bits between the data output of an orthogonal transformer and the data input of an encoder for encoding the data output of the orthogonal transformer.

Abstract: A specific section provided in a track is set in a DC free state, and during reproducing, accurate tracking is conducted on the basis of the crosstalk from the pilot tone superposed in the adjacent tracks in this DC free section. Alternatively, a pilot tone is generated only in a specific section provided in the track, and when reproducing, accurate tracking is effected on the basis of the crosstalk of the pilot tone in the tracks adjacent to this section. As a result, the redundancy required for tracking is notably reduced.

Abstract: A record unit of coded video data is concealed. The record unit is reproduced from a recording medium and has a first recording block containing a part of a coded video data A which has been obtained by coding m blocks of video data among a plurality of blocks of video data divided from video data of one page, a second recording block containing a part of a coded video data B which has been obtained by coding other m blocks of video data among the plurality of blocks of video data and a third recording block containing in a first part thereof the remaining part of the coded video data A and in a second part thereof the remaining part of the coded video data B. The record unit also contains an address data indicating an address of a border of the first and second parts of the third recording block.

Abstract: In a method of recording digital signals, in which all audio signals of N channels (N=integer) are recorded on M tracks (M=integer>N) where video signals of I fields (I=integer) are recorded, the improvement including: the M tracks being divided into N track groups each having S tracks (S=integer=M/N) arranged successively such that the audio signals of a j-th channel (j=integer) in the N channels are recorded on the tracks of an i-th track group (i=integer) in the N track groups.

Abstract: When dividing a video signal composed of horizontal H pixels and vertical V pixels into blocks of (m.times.n) pixels composed of horizontal m pixels and vertical n pixels, when the number of horizontal pixels or the number of vertical pixels is not equal to an integer multiple of m or n, respectively, the video signal is first divided into blocks of (m.times.n) pixels and sub-blocks of a smaller size. Then, a plurality of sub-blocks are put together to make up a block of (m.times.n) pixels.