Patents by Inventor Tatsuro Kikuchi

Tatsuro Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973159
    Abstract: Provided is a photodetector which can be manufactured in a standard process of a mass-produced CMOS foundry. The photodetector includes a silicon (Si) substrate; a lower clad layer; a core layer including a waveguide layer configured to guide signal light, and including a first Si slab doped with first conductive impurity ions and a second Si slab doped with second conductive impurity ions; a germanium (Ge) layer configured to absorb light and including a Ge region doped with the first conductive impurity ions; an upper clad layer; and electrodes respectively connected to the first and second Si slabs and the Ge region. A region of the core layer sandwiched between the first Si slab and the second Si slab operates as an amplification layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 30, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Kotaro Takeda, Kiyofumi Kikuchi, Yoshiho Maeda, Tatsuro Hiraki
  • Patent number: 6437579
    Abstract: A method for screening multi-layered ceramic capacitors having internal defects at a high accuracy by superposing a direct-current constant current between external electrodes of a multi-layered ceramic capacitor having a defective part in an effective layer of the dielectric ceramic, raising the voltage between the external electrodes, and further feeding the direct-current constant current for a specific time after the voltage curve becomes flat, capacitors experiencing a sudden drop in the voltage between the external electrodes during the feeding time are sorted out and removed as a defective product.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: August 20, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukihito Yamashita, Akira Omi, Takeshi Iino, Shigeki Inagaki, Tatsuro Kikuchi, Yoshinori Tomita
  • Patent number: 5122860
    Abstract: Provided is an integrated circuit device is used in an IC card or the like, and a manufacturing method of the integrated circuit device, having a thin thickness so as to be capable of being manufactured highly accurately in dimensions and highly efficiently. The integrated circuit element (12) is mounted on one surface of the thin metal plates (11) having the other surface which at least part serves as a plurality of external connecting terminals (11a) and, on one surface side, the integrated circuit element (12) is covererd with a sealing resin (15).
    Type: Grant
    Filed: September 20, 1990
    Date of Patent: June 16, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tatsuro Kikuchi, Yoshitsugu Uenishi
  • Patent number: 5014158
    Abstract: A laminated ceramic capacitor comprises a plurality of inner electrode layers for developing a capacitance, dielectric layers sandwiched with the inner electrode layers, and a pair of outer electrodes coupled to their associated inner electrode layers for output of the capacitance. The inner electrode layers are made of Ni. The dielectric layers are made of a dielectric ceramic composition having a structural formula of:{Bam(Til-xZrx)O2+m}1-.alpha.-.beta.-{MnO2}.alpha.-{X}.beta.where X is at least one of Yb2O3, Dy2O3, and ThO2 and m, x, .alpha., and .beta. are expressed as:0.98.ltoreq.m.ltoreq.1.020.ltoreq.x.ltoreq.0.20.005.ltoreq..alpha..ltoreq.0.050.001.ltoreq..beta..ltoreq.0.02so that the laminated ceramic capacitor can be minimized in the size, increased in the capacitance, and reduced in the cost of production.
    Type: Grant
    Filed: April 11, 1990
    Date of Patent: May 7, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsutomu Nishimura, Seiichi Nakatani, Satoru Yuhaku, Yasuhiko Hakotani, Tatsuro Kikuchi
  • Patent number: 4863683
    Abstract: A manufacturing method for a multilayered ceramic body using Cu, Ni, Co or Fe as a conductor material, and a conductor forming paste of particular composition of CuO, NiO, CoO or Fe.sub.2 O.sub.3 as the main component, the paste being applied to the multilayered body. The manufacturing method comprises: a process of forming the multilayered body with conductor paste of CuO, NiO, CoO or Fe.sub.2 O.sub.3 as the main component and insulating paste formed of glass and/or ceramic, so that a binder is removed from the laminate by heat treatment in an oxidizing atmosphere; a process of heat treatment for reducing the oxide; and a sintering process for sintering the laminate in a nitrogen atmosphere.
    Type: Grant
    Filed: June 24, 1987
    Date of Patent: September 5, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Satoru Yuhaku, Hideyuki Okinaka, Toru Ishida, Osamu Makino, Tatsuro Kikuchi
  • Patent number: 4714570
    Abstract: A manufacturing method for a multilayered ceramic body using Cu, Ni, Co or Fe as a conductor material, and a conductor forming paste of a particular composition of CuO, NiO, CoO or Fe.sub.2 O.sub.3 as the main component, the paste being applied to the multilayered body. The manufacturing method comprises: a process of forming the multilayered body with conductor paste of CuO, NiO, CoO or Fe.sub.2 O.sub.3 as the main component and insulating paste formed of glass and/or ceramic, so that a binder is removed from the laminate by heat treatment in an oxidizing atmosphere; a process of heat treatment for reducing the oxide; and a sintering process for sintering the laminate in a nitrogen atmosphere.
    Type: Grant
    Filed: July 17, 1985
    Date of Patent: December 22, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Satoru Yuhaku, Hideyuki Okinaka, Toru Ishida, Osamu Makino, Tatsuro Kikuchi
  • Patent number: 4495546
    Abstract: A hybrid integrated circuit component for insertion in a slit of a mother printed circuit board, and a method of mounting the hybrid integrated circuit component. The circuit component includes a flexible circuit board composed of a flexible insulated substrate, a circuit conductor formed on one side of the substrate, and a pair of conductor layers formed along opposite sides of the substrate to serve as external connection terminals. Circuit elements are mounted on the substrate and electrically connected to the circuit conductor.
    Type: Grant
    Filed: May 13, 1982
    Date of Patent: January 22, 1985
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsuneshi Nakamura, Tatsuro Kikuchi
  • Patent number: 4169026
    Abstract: An etchant comprising an electrolytic liquid which comprises sulfuric acid as a main component and water in such amount that the weight ratio of sulfuric acid to water is between 9:1 and 2:1. The ferrite surface having been electrolytically etched by using this etchant is smooth. Thus, this etchant makes it possible to etch a ferrite to a large depth, and thereby easily shape a ferrite by electrolytic etching, e.g. to define the track width of a magnetic head.
    Type: Grant
    Filed: July 10, 1978
    Date of Patent: September 25, 1979
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tatsuro Kikuchi, Kenichi Fujimura, Hyogo Hirohata, Tetsuo Hino