Abstract: The invention makes it possible to efficiently and accurately supply parts to a work in an assembling production line structured as a mixed assembly line, and to improve a flexibility of changing the line.

Abstract: A semiconductor arithmetic unit which realizes a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor is composed of a binary-multivalue-analog merged operation processing circuit. A multi-loop circuit includes an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which first electrodes and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group.

Abstract: The invention makes it possible to efficiently and accurately supply parts to a work in an assembling production line structured as a mixed assembly line, and to improve a flexibility of changing the line.

Abstract: A host computer writes a page code corresponding to a desired page in page designation areas R1 to R32 in a brief datalink area P in a communication packet so as to receive necessary detailed information from each of producing machines #1 to #32, and sends the communication packet to the producing machines. Each producing machine always supervises the page designation areas R1 to R32 in the communication packet received from the host computer. Further, each producing machine writes the detailed information of a page corresponding to the page code written in the data designation areas R1 to R32 in a detailed datalink area Q as well as writes a page code of the page of the detailed information, written in the detailed datalink area Q, in the page designation areas R1 to R32. Thereby, it is possible to interchanges necessary information between the host computer and each of the plurality of producing machines at high speed.