Patents by Inventor Tatsuro Osada

Tatsuro Osada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250078447
    Abstract: A monitoring device includes a memory; and a processor configured to execute a process including acquiring image data indicating a change in intensity of incident light from a sensor array, determining a first region to be monitored and a second region not to be monitored in a field of view of the sensor array, and outputting a monitoring result of a moving object based on the image data acquired by the sensor array in the first region.
    Type: Application
    Filed: June 20, 2024
    Publication date: March 6, 2025
    Inventors: Soichi HAGIWARA, Tatsuro OSADA
  • Patent number: 8294241
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: October 23, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tatsuro Osada, Kaoru Saigoh
  • Publication number: 20110198724
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 18, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tatsuro OSADA, Kaoru SAIGOH
  • Patent number: 7955944
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tatsuro Osada, Kaoru Saigoh
  • Publication number: 20090267185
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 29, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Tatsuro Osada, Kaoru Saigoh