Patents by Inventor Tatsuro SHINOZAKI

Tatsuro SHINOZAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device
    Patent number: 10283647
    Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 7, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Koji Matsuo, Gaku Sudo, Jun Nogami, Tatsuro Shinozaki, Takashi Ishida, Jun Fujiki, Kenzo Manabe
  • SEMICONDUCTOR DEVICE
    Publication number: 20180040742
    Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 8, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Koji Matsuo, Gaku Sudo, Jun Nogami, Tatsuro Shinozaki, Takashi Ishida, Jun Fujiki, Kenzo Manabe
  • Pattern forming method
    Patent number: 9880464
    Abstract: According to one embodiment, an imprint pattern forming method includes providing a substrate with a pattern formation region and a peripheral region, the peripheral region having a surface lower than a surface of the pattern formation region, located at a periphery of the pattern formation region. The method includes forming an auxiliary pattern with a predetermined height on at least a portion of the peripheral region, providing a resist layer on at least the pattern formation region, and imprinting the resist layer using a template by locating the template in a region which includes a portion of the pattern formation region and a portion of the peripheral region.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Kawamura, Koji Matsuo, Masanobu Baba, Tatsuro Shinozaki, Taishi Ishikura
  • PATTERN FORMING METHOD
    Publication number: 20170184958
    Abstract: According to one embodiment, an imprint pattern forming method includes providing a substrate with a pattern formation region and a peripheral region, the peripheral region having a surface lower than a surface of the pattern formation region, located at a periphery of the pattern formation region. The method includes forming an auxiliary pattern with a predetermined height on at least a portion of the peripheral region, providing a resist layer on at least the pattern formation region, and imprinting the resist layer using a template by locating the template in a region which includes a portion of the pattern formation region and a portion of the peripheral region.
    Type: Application
    Filed: August 26, 2016
    Publication date: June 29, 2017
    Inventors: Daisuke KAWAMURA, Koji MATSUO, Masanobu BABA, Tatsuro SHINOZAKI, Taishi ISHIKURA
  • Fabric material
    Patent number: 9637843
    Abstract: A stainless wire that does not have a crystal grain of 200 nm or greater in maximum length in a surface normal to a fiber axis within a range of 1 ?m square from a center of a diameter in a cross section normal to a fiber axial direction is used as the stainless wire that forms a fabric material.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: May 2, 2017
    Assignee: TOYOTA BOSHOKU KABUSHIKI KAISHA
    Inventors: Hideaki Kunisada, Yoshiteru Honma, Hiroki Kashima, Miki Imai, Tatsuro Shinozaki, Masako Furuta
  • FABRIC MATERIAL
    Publication number: 20140363656
    Abstract: A stainless wire that does not have a crystal grain of 200 nm or greater in maximum length in a surface normal to a fiber axis within a range of 1 ?m square from a center of a diameter in a cross section normal to a fiber axial direction is used as the stainless wire that forms a fabric material.
    Type: Application
    Filed: June 6, 2013
    Publication date: December 11, 2014
    Inventors: Hideaki KUNISADA, Yoshiteru HONMA, Hiroki KASHIMA, Miki IMAI, Tatsuro SHINOZAKI, Masako FURUTA