Patents by Inventor Tatsuro Toya
Tatsuro Toya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10074660Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.Type: GrantFiled: February 19, 2016Date of Patent: September 11, 2018Assignee: FLOADIA CORPORATIONInventors: Hideo Kasai, Yasuhiro Taniguchi, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Tatsuro Toya, Takanori Yamaguchi, Fukuo Owada, Shinji Yoshida, Teruo Hatada, Satoshi Noda, Takafumi Kato, Tetsuya Muraya, Kosuke Okuyama
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Patent number: 10074658Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.Type: GrantFiled: March 18, 2016Date of Patent: September 11, 2018Assignee: FLOADIA CORPORATIONInventors: Yutaka Shinagawa, Yasuhiro Taniguchi, Hideo Kasai, Ryotaro Sakurai, Yasuhiko Kawashima, Tatsuro Toya, Kosuke Okuyama
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Patent number: 10038101Abstract: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.Type: GrantFiled: October 6, 2015Date of Patent: July 31, 2018Assignee: FLOADIA CORPORATIONInventors: Yutaka Shinagawa, Yasuhiro Taniguchi, Hideo Kasai, Ryotaro Sakurai, Yasuhiko Kawashima, Tatsuro Toya, Kosuke Okuyama
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Publication number: 20180083014Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.Type: ApplicationFiled: March 18, 2016Publication date: March 22, 2018Inventors: Yutaka SHINAGAWA, Yasuhiro TANIGUCHI, Hideo KASAI, Ryotaro SAKURAI, Yasuhiko KAWASHIMA, Tatsuro TOYA, Kosuke OKUYAMA
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Publication number: 20180019248Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.Type: ApplicationFiled: February 19, 2016Publication date: January 18, 2018Inventors: Hideo KASAI, Yasuhiro TANIGUCHI, Yasuhiko KAWASHIMA, Ryotaro SAKURAI, Yutaka SHINAGAWA, Tatsuro TOYA, Takanori YAMAGUCHI, Fukuo OWADA, Shinji YOSHIDA, Teruo HATADA, Satoshi NODA, Takafumi KATO, Tetsuya MURAYA, Kosuke OKUYAMA
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Patent number: 9842650Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.Type: GrantFiled: July 22, 2015Date of Patent: December 12, 2017Assignee: FLOADIA CORPORATIONInventors: Yasuhiro Taniguchi, Yutaka Shinagawa, Hideo Kasai, Ryotaro Sakurai, Tatsuro Toya, Yasuhiko Kawashima, Kosuke Okuyama
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Publication number: 20170222036Abstract: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.Type: ApplicationFiled: October 6, 2015Publication date: August 3, 2017Inventors: Yutaka Shinagawa, Yasuhiro Taniguchi, Hideo Kasai, Ryotaro Sakurai, Yasuhiko Kawashima, Tatsuro Toya, Kosuke Okuyama
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Publication number: 20170221563Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.Type: ApplicationFiled: July 22, 2015Publication date: August 3, 2017Inventors: Yasuhiro Taniguchi, Yutaka Shinagawa, Hideo Kasai, Ryotaro Sakurai, Tatsuro Toya, Yasuhiko Kawashima, Kosuke Okuyama
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Patent number: 5583381Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.Type: GrantFiled: September 28, 1995Date of Patent: December 10, 1996Assignee: Hitachi, Ltd.Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
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Patent number: 5552639Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.Type: GrantFiled: June 1, 1995Date of Patent: September 3, 1996Assignee: Hitachi, Ltd.Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
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Patent number: 5539257Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.Type: GrantFiled: June 1, 1995Date of Patent: July 23, 1996Assignee: Hitachi, Ltd.Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
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Patent number: 5468998Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.Type: GrantFiled: August 22, 1994Date of Patent: November 21, 1995Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
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Patent number: 5371411Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.Type: GrantFiled: June 7, 1993Date of Patent: December 6, 1994Assignee: Hitachi, Ltd.Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
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Patent number: 5229642Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.Type: GrantFiled: May 21, 1991Date of Patent: July 20, 1993Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
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Patent number: 5087915Abstract: A single-chip microcomputer is comprised of an analog to digital converter, a first external terminal which receives an analog signal which is to be converted by the analog to digital converter, and a second external terminal for receiving a signal indicating an operating condition of the analog to digital converter.Type: GrantFiled: January 2, 1990Date of Patent: February 11, 1992Assignee: Hitachi, Ltd., & Hitachi Microcomputer Engineering Ltd.Inventor: Tatsuro Toya
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Patent number: 5023699Abstract: A resin molded type semiconductor device has a metallic ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the ring.Type: GrantFiled: October 10, 1989Date of Patent: June 11, 1991Assignee: Hitachi, Ltd.Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
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Patent number: 4625227Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.Type: GrantFiled: June 13, 1985Date of Patent: November 25, 1986Assignees: Hitachi, Ltd, Hitachi Microcomputer Engineering, Ltd.Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya