Patents by Inventor Tatsuro Watahiki

Tatsuro Watahiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200185541
    Abstract: An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer.
    Type: Application
    Filed: June 8, 2018
    Publication date: June 11, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yohei YUDA, Tatsuro WATAHIKI, Akihiko FURUKAWA
  • Publication number: 20200127099
    Abstract: A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.
    Type: Application
    Filed: February 10, 2017
    Publication date: April 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuro HAYASHIDA, Takuma NANJO, Tatsuro WATAHIKI, Akihiko FURUKAWA
  • Patent number: 10483110
    Abstract: A p-type oxide semiconductor is prevented from being oxidized by oxygen in an n-type oxide semiconductor even if the p-type oxide semiconductor is provided as a termination structure in the n-type oxide semiconductor. A semiconductor device includes an n-type gallium oxide substrate, an anode electrode joined to the n-type gallium oxide substrate, and a cathode electrode provided on the n-type gallium oxide substrate. Current flows between the anode electrode and the cathode electrode via the n-type gallium oxide substrate provided between the anode electrode and the cathode electrode. The semiconductor device further includes a p-type oxide semiconductor layer provided adjacent to a junction between the anode electrode and the n-type gallium oxide substrate, and a nitride layer provided between the p-type oxide semiconductor layer and the n-type gallium oxide substrate.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: November 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yohei Yuda, Tatsuro Watahiki
  • Publication number: 20190267237
    Abstract: A p-type oxide semiconductor is prevented from being oxidized by oxygen in an n-type oxide semiconductor even if the p-type oxide semiconductor is provided as a termination structure in the n-type oxide semiconductor. A semiconductor device includes an n-type gallium oxide substrate, an anode electrode joined to the n-type gallium oxide substrate, and a cathode electrode provided on the n-type gallium oxide substrate. Current flows between the anode electrode and the cathode electrode via the n-type gallium oxide substrate provided between the anode electrode and the cathode electrode. The semiconductor device further includes a p-type oxide semiconductor layer provided adjacent to a junction between the anode electrode and the n-type gallium oxide substrate, and a nitride layer provided between the p-type oxide semiconductor layer and the n-type gallium oxide substrate.
    Type: Application
    Filed: June 8, 2017
    Publication date: August 29, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yohei YUDA, Tatsuro WATAHIKI
  • Publication number: 20170330990
    Abstract: A method for manufacturing a photovoltaic device capable of suppressing decreases in an open-circuit voltage and a fill factor or suppressing the occurrence of a current leak. The method for manufacturing a photovoltaic device includes: (a) forming a pyramidal texture on a first main surface of a silicon substrate; (b) forming a first silicate glass on the first main surface; (c) forming a second silicate glass on the first silicate glass; (d) diffusing the impurities of the first conductivity type contained in the first silicate glass to the first main surface of the silicon substrate; (e) forming a third silicate glass on the second silicate glass; and (f) diffusing impurities of a second conductivity type to a second main surface of the silicon substrate after (e).
    Type: Application
    Filed: May 11, 2015
    Publication date: November 16, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takehiko SATO, Kunihiko NISHIMURA, Shinya NISHIMURA, Tatsuro WATAHIKI
  • Publication number: 20150270419
    Abstract: A photoelectric conversion element includes: a photoelectric conversion layer; and first and second electrodes formed on surfaces of the photoelectric conversion layer, wherein at least one of the first and second electrodes includes a translucent conductive base layer made of a translucent conductive material, and a translucent conductive mesh layer selectively buried in the translucent conductive base layer, having electrical resistivity lower than electrical resistivity of the translucent conductive base layer, and formed in a translucent conductive film pattern.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 24, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yohei YUDA, Takayuki MORIOKA, Tsutomu MATSUURA, Tatsuro WATAHIKI
  • Publication number: 20150214393
    Abstract: A solar cell is provided that includes: a solar-battery cell that has a pn junction; a light-receiving-surface side electrode that includes a plurality of grid electrodes that are provided so as to extend in one direction at a given spacing on a light receiving surface of the solar-battery cell, and that collect a photoelectrically-converted charge; and a back-surface electrode that is provided on a back surface that opposes to the light receiving surface of the solar-battery cell. The grid electrode includes a first seed surface that comes into contact with the light receiving surface of the solar-battery cell, a second seed surface that is upright to the first seed surface, and is connected to the first seed surface, and a plated layer that comes into contact with the first seed surface and the second seed surface.
    Type: Application
    Filed: January 22, 2015
    Publication date: July 30, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuro HAYASHIDA, Tatsuro WATAHIKI, Tsutomu MATSUURA, Takayuki MORIOKA
  • Publication number: 20150214398
    Abstract: A first amorphous silicon i layer and an amorphous silicon p layer are provided on a first main surface, side surfaces, and a peripheral portion of a second main surface of an n-type silicon substrate. A first ITO layer is provided over the first main surface and the side surfaces, a second amorphous silicon i layer and an amorphous silicon n layer are provided on the second main surface, and a second ITO layer having a smaller area than the n-type silicon substrate is provided thereon excluding the peripheral portion. On the peripheral portion of the second main surface, a structure, in which the first amorphous silicon i layer, the amorphous silicon p layer, the second amorphous silicon i layer, and the amorphous silicon n layer are laminated in this order, is provided.
    Type: Application
    Filed: August 27, 2013
    Publication date: July 30, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tatsuro Watahiki, Shuichi Hiza, Takehiko Sato
  • Publication number: 20100189897
    Abstract: An evaporator cell (100), which is adapted for evaporating, in particular, a high-melting evaporant, includes a crucible (10) for receiving the evaporant, said crucible including a crucible bottom (11), a side wall (12) which extends in an axial direction of the crucible (10), and a crucible opening (13), and a heating device (20) with a heating resistor (21), which has a plurality of heating zones (21.1, 21.2), which are arranged on an outside surface of the crucible (10) and extend axially along the crucible (10), wherein the heating zones (21.1, 21.2) are equipped for multilateral resistance heating and/or electron beam heating of the crucible (10), and wherein the heating zones (21.1, 21.2) are constructed in such a manner that a heating current through the heating resistor (21), which is formed for example by a resistance sleeve, flows in parallel and in the same sense through all heating zones (21.1, 21.2). A method of operating the evaporator cell is also described.
    Type: Application
    Filed: July 21, 2008
    Publication date: July 29, 2010
    Applicants: CREATEC FISCHER & CO. GMBH, FORSCHUNGSVERBUND BERLIN E.V.
    Inventors: Wolfgang Braun, Albrecht Fischer, Tatsuro Watahiki