Abstract: In a radio receiver for receiving a radio signal, a counter (32) counts an eventual intermediate frequency of an amplified signal based on a reference signal as a count datum. A frequency controller (27) controls a reference frequency of the reference signal according to the count datum. A reference oscillator (25) is controlled by the frequency controller to produce the reference signal. Receiving a radio signal by double superheterodyne, the radio receiver gives the eventual intermediate frequency to the amplified signal. In the amplified signal, the frequency controller suppresses an eventual frequency drift which results from frequency drifts of a first local oscillation and a second local oscillation. The radio receiver may be a single superheterodyne receiver.

Abstract: A printed circuit board allowing the characteristic impedance and wavelength compaction ratio of microstrip lines thereof measured without disconnecting them from surrounding circuitry. A strip conductor has a land for measurement at one end thereof and chip lands connectable to a chip resistor at the other end.

Abstract: A frequency synthesizer, which realizes speed-up of channel switching between channels having separated frequencies, has an EEPROM which stores the phase difference between a first frequency divider and a second frequency divider producing outputs corresponding to the frequencies of the channels to be switched. A delay circuit delays the output of the second frequency divider by an amount corresponding to an amount of the phase difference stored in the EEPROM. A controller supplies the outputs of the second frequency divider and the delay circuit to a phase detector. Further, the controller stops a PLL operation and restarts it in synchronism with a leading edge of, preferably, a second period of the output signal of the reference oscillator to which the preset phase difference is given.

Abstract: A transmitter using a gallium arsenide FET in a power amplifier and having a biassing circuit for generating a gate biassing voltage for the FET, a first power supply for supplying a first power to the biassing circuit and a second power supply for supplying a second power to the power amplifier, the second power being higher in voltage than the first power and being produced at a time delay from production of the first power at a start condition of the transmitter, wherein the first power is supplied to the biassing circuit through a first diode with a voltage drop to thereby reduce the gate biassing voltage below a normal one so that an undesired signal is suppressed at the power amplifier. The second power is delivered to the biassing circuit through a second diode so that the biassing circuit is driven by the second power to produce the normal biassing voltage.

Abstract: A frequency modulator utilizing a frequency synthesizer is disclosed. The modulator is especially useful in a mobile radio communication apparatus. The synthesizer includes a phase locked loop made up of a voltage controlled oscillator (VCO), a programmable frequency divider, a phase comparator, a second frequency divider, a reference oscillator, and a low-pass filter. When a channel control signal is input to the programmable frequency divider, the modulator sensitivity of the voltage controlled oscillator is undesirably deviated according to the channel selection. An increase of the modulator sensitivity due to an increase of the oscillation frequency is compensated for by adding a simple FET to the VCO bias circuit. A control voltage from the phase locked loop is applied to both the voltage controlled oscillator and its bias circuit.

Abstract: A diversity reception radio receiver has a two-receiver system incorporating first and second receivers. A wave envelope detector is provided for each receiver to generate an output voltage corresponding to the strength of the electromagnetic signal wave which is picked up by the receiver. A hysteresis comparator compares the outputs of the two wave envelope detectors and generates a switching control signal. A switching device responds to the switching control signal by selecting between the signals which are repoduced by the first and second receivers. Because the amount of hysteresis in the comparator is automatically adjusted in accord with the strength of the signal wave, there is a minimum of hunting between the outputs of the two receivers.

Abstract: A phase locked loop frequency synthesizer comprises a voltage-controlled oscillator (VCO) for generating a signal having a frequency which varies in response to a control voltage. A variable frequency divider divides the output frequency of the VCO in a ratio which is determined by a control signal. A reference oscillator supplies a reference signal having a predetermined frequency. A fixed frequency divider divides the frequency of the reference signal in a fixed ratio. A phase comparator compares the phases of the outputs of the fixed frequency divider and variable frequency divider to provide a control pulse corresponding to a phase difference between these outputs. A charge pump has a power supply terminal for generating a charge/discharge voltage in response to the control pulse. A loop filter includes a first capacitor which is supplied with the charge/discharge voltage for supplying a control voltage to the VCO which corresponds to the charge/discharge voltage. A power supply circuit generates a D.C.