Abstract: A serial interface circuit, a semiconductor device, and a serial-parallel conversion method are provided. The disclosure is to generate first to nth timing signals respectively indicating timings that differ by 1 bit cycle of the bit string when receiving a serial signal including the bit string in a serial form and converting the bit string into a parallel form to obtain a parallel bit group. Each bit in the bit string is held at the timings of the first to tth timing signals as the standby bit group, the standby bit group is acquired at the timing of any one of the (t+1)th to nth timing signals as a part of the parallel bit group, and each bit in the bit string is held at the timings of the (t+1)th to nth timing signals and the held bit group is set as another part of the parallel bit group.

Abstract: A serial interface circuit, a semiconductor device, and a serial-parallel conversion method are provided. The disclosure is to generate first to nth timing signals respectively indicating timings that differ by 1 bit cycle of the bit string when receiving a serial signal including the bit string in a serial form and converting the bit string into a parallel form to obtain a parallel bit group. Each bit in the bit string is held at the timings of the first to tth timing signals as the standby bit group, the standby bit group is acquired at the timing of any one of the (t+1)th to nth timing signals as a part of the parallel bit group, and each bit in the bit string is held at the timings of the (t+1)th to nth timing signals and the held bit group is set as another part of the parallel bit group.

Abstract: A semiconductor memory device and a data reading method capable of appropriately reading data stored in memory cells are provided. The semiconductor memory device includes: a memory cell array including multiple memory cells and having a known-data storage area storing determination data used for determining appropriateness or inappropriateness of a value of each of a reading voltage applied to a memory cell when reading data stored in the memory cell and a comparative current used for a comparison with a current flowing through a memory cell according to stored data; a decoder that applies the reading voltage to a memory cell to be read according to an address representing the memory cell to be read; and a sense amplifier including a comparison circuit that outputs a comparison result acquired by comparing a current flowing through the memory cell to be read 66 according to stored data with the comparative current.

Abstract: A semiconductor memory device and a data reading method capable of appropriately reading data stored in memory cells are provided. The semiconductor memory device includes: a memory cell array including multiple memory cells and having a known-data storage area storing determination data used for determining appropriateness or inappropriateness of a value of each of a reading voltage applied to a memory cell when reading data stored in the memory cell and a comparative current used for a comparison with a current flowing through a memory cell according to stored data; a decoder that applies the reading voltage to a memory cell to be read according to an address representing the memory cell to be read; and a sense amplifier including a comparison circuit that outputs a comparison result acquired by comparing a current flowing through the memory cell to be read 66 according to stored data with the comparative current.

Abstract: A semiconductor memory has main bit lines paralleled by fixed potential lines in an alternating arrangement. Each main bit line is switchably connected to two sub-bit lines. The memory cells connected to one of the two sub-bit lines are placed below the main bit line. The memory cells connected to the other one of the two sub-bit lines are placed below an adjacent fixed potential line. The fixed potential lines prevent parasitic capacitive coupling between the main bit lines and thereby speed up read access to the memory cells without taking up extra layout space.

Abstract: A semiconductor memory has main bit lines paralleled by fixed potential lines in an alternating arrangement. Each main bit line is switchably connected to two sub-bit lines. The memory cells connected to one of the two sub-bit lines are placed below the main bit line. The memory cells connected to the other one of the two sub-bit lines are placed below an adjacent fixed potential line. The fixed potential lines prevent parasitic capacitive coupling between the main bit lines and thereby speed up read access to the memory cells without taking up extra layout space.

Abstract: There is provided a nonvolatile semiconductor memory wherein a normal mode voltage is provided to a selected word line when a normal mode is selected, and a test mode voltage lower than the normal mode voltage is provided to the selected word line when a test mode is selected, thus leakage current is detected by selecting the test mode.

Abstract: There is provided a nonvolatile semiconductor memory wherein a normal mode voltage is provided to a selected word line when a normal mode is selected, and a test mode voltage lower than the normal mode voltage is provided to the selected word line when a test mode is selected, thus leakage current is detected by selecting the test mode.