Patents by Inventor Tatsushi Hakuchoh

Tatsushi Hakuchoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7480824
    Abstract: When a testing system is connected to a debug port of a tape drive unit or a SCSI bus, a self-checking test for a fabricating process is executed. When the testing system is not connected, the self-checking test for normal operation is executed. And in a test of a single card, a motor test and an MR head resistance test, which are tests of a mechanical structure portion, are omitted. In addition, in a box assembling process, the test contents are suppressed to a minimum prior to adjustments to the, tape head. Furthermore, in a test program, the status of a flag or an indication corresponding to a test executed in a next step is changed.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: January 20, 2009
    Assignee: International Business Machines Corporation
    Inventors: Tatsushi Hakuchoh, Tomoaki Kimura, Tsuyoshi Miyamura
  • Publication number: 20050166093
    Abstract: When a testing system is connected to a debug port of a tape drive unit or a SCSI bus, a self-checking test for a fabricating process is executed. When the testing system is not connected, the self-checking test for normal operation is executed. And in a test of a single card, a motor test and an MR head resistance test, which are tests of a mechanical structure portion, are omitted. In addition, in a box assembling process, the test contents are suppressed to a minimum prior to adjustments to the, tape head. Furthermore, in a test program, the status of a flag or an indication corresponding to a test executed in a next step is changed.
    Type: Application
    Filed: February 23, 2005
    Publication date: July 28, 2005
    Inventors: Tatsushi Hakuchoh, Tomoaki Kimura, Tsuyoshi Miyamura
  • Patent number: 6915453
    Abstract: When a testing system is connected to a debug port of a tape drive unit or a SCSI bus, a self-checking test for a fabricating process is executed. When the testing system is not connected, the self-checking test for normal operation is executed. And in a test of a single card, a motor test and an MR head resistance test, which are tests of a mechanical structure portion, are omitted. In addition, in a box assembling process, the test contents are suppressed to a minimum prior to adjustments to the tape head. Furthermore, in a test program, the status of a flag or an indication corresponding to a test executed in a next step is changed.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: July 5, 2005
    Assignee: International Business Machines Corporation
    Inventors: Tatsushi Hakuchoh, Tomoaki Kimura, Tsuyoshi Miyamura
  • Publication number: 20020018379
    Abstract: When a testing system is connected to a debug port of a tape drive unit or a SCSI bus, a self-checking test for a fabricating process is executed. When the testing system is not connected, the self-checking test for normal operation is executed. And in a test of a single card, a motor test and an MR head resistance test, which are tests of a mechanical structure portion, are omitted. In addition, in a box assembling process, the test contents are suppressed to a minimum prior to adjustments to the tape head. Furthermore, in a test program, the status of a flag or an indication corresponding to a test executed in a next step is changed.
    Type: Application
    Filed: July 6, 2001
    Publication date: February 14, 2002
    Inventors: Tatsushi Hakuchoh, Tomoaki Kimura, Tsuyoshi Miyamura