Abstract: A shift arithmetic device which has a circulating shifter for shifting N-bit information by a specified number of bits and a set circuit for setting logic "O" or "1" in the shifted N-bit information at the bit positions corresponding to the specified number of bits shifted. A memory having stored therein N-bit patterns whose arrangements of logic "0" and "1" sequentially change and a bit arithmetic unit for executing logical processing, for each bit, between N-bit pattern read from an address of the memory corresponding to the number of bits shifted and N-bit information shifted by the circulating shifter.

Abstract: A control system for a plurality of I/O apparatuses used for transferring data between a main memory and an I/O apparatus controlling device through a channel control device. If an error occurs in the data transfer, no response signal is sent to the I/O apparatus controlling device from the channel control device and the absence of the response signal is detected by time supervision in the supervising circuit in the I/O apparatus controlling device, so that only the portion of the I/O apparatus related to the error is stopped.