Abstract: A method of allowing exclusive access to shared data by a computing device and a computer readable article embodying instructions for executing the method. The method includes: reading from a storage unit into a memory a program including a code for execution in a critical section and an instruction to write a value into or read a value from a shared data area in the memory; acquiring a lock on the critical section before start of a first instruction in the critical section; writing a value into a thread-local area in the memory in response to an instruction to write the value into the shared data area; writing into the shared data area the value written into the thread-local area upon completion of a final instruction in the critical section; and releasing the lock on the critical section, thereby allowing exclusive access to shared data.

Abstract: The present invention relates to allocating registers to variables in order to compile a program. In an embodiment of the present invention a compiler apparatus stores interference information indicating an interference relationship between variables, selects a register and allocates the register to each variables in accordance with a predetermined procedure, without allocating the same register to a set of variables having interference relationships. The compiler further replaces multiple variables having the same register allocated thereto with a new variable and generates an interference relationship by merging the interference relationships each concerning one of multiple variables.

Abstract: A method of allowing exclusive access to shared data by a computing device and a computer readable article embodying instructions for executing the method. The method includes: reading from a storage unit into a memory a program including a code for execution in a critical section and an instruction to write a value into or read a value from a shared data area in the memory; acquiring a lock on the critical section before start of a first instruction in the critical section; writing a value into a thread-local area in the memory in response to an instruction to write the value into the shared data area; writing into the shared data area the value written into the thread-local area upon completion of a final instruction in the critical section; and releasing the lock on the critical section, thereby allowing exclusive access to shared data.

Abstract: The present invention relates to allocating registers to variables in order to compile a program. In an embodiment of the present invention a compiler apparatus stores interference information indicating an interference relationship between variables, selects a register and allocates the register to each variables in accordance with a predetermined procedure, without allocating the same register to a set of variables having interference relationships. The compiler further replaces multiple variables having the same register allocated thereto with a new variable and generates an interference relationship by merging the interference relationships each concerning one of multiple variables.

Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.

Abstract: A method and system are provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.

Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.

Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.

Abstract: A program optimization method for converting program source code written in a programming language into machine language includes steps of: analyzing a target program and detecting an exception generative instruction, which may generate an exception, and exception generation detection instructions, which brunches a process to an exception process when an exception occurrence condition is detected and an exception has occurred.

Abstract: A compiler that optimizes a program to be compiled includes: an order constraint information obtaining unit that obtains order constraint information defined among a plurality of instructions; an order determination unit that sequentially determines the execution order for each of the plurality of instructions based on the order constraint information; a unit for analyzing the number of registers that analyzes the number of required registers, which is the number of registers that will be required when the instructions with its execution order determined are executed; an instruction detection unit that detects a combination of two instructions, in which one instruction is a determined-order instruction, the other instruction is an undetermined-order instruction, and the order constraint information does not include a constraint that the one instruction should be executed before the other instruction; and an order determination reprocessing unit that, when the number of required registers exceeds a predetermin

Abstract: The present invention optimizes program execution by reducing previous restrictions for an exception generative instruction for another instruction, so that the parallelisms of the instructions of a program, including exception generative instructions, can be effectively obtained. Preferably, the novel compiler comprises: a DAG (directed acyclic graph) generator for analyzing quadruple intermediate code in a target program and for generating a DAG; a DAG editing unit for editing the DAG and for reducing for the operators order restrictions due to the occurrence of an exception; and a quadruple intermediate code reproduction unit for generating quadruple intermediate code which reflects the structure of the obtained DAG. An exception generative instruction and an exception generation detection instruction are thus detected.