Patents by Inventor Tatsushi Kato

Tatsushi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230399778
    Abstract: A heat insulating, heat storing, and heat generating material includes first fibers having a function of generating heat through moisture absorption, second fibers having a diameter smaller than a diameter of the first fibers, and a binding material binding together the first fibers, binding together the second fibers, and binding together the first fibers and the second fibers. The binding material contains a thermoplastic resin.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 14, 2023
    Inventors: Satomi YOSHIOKA, Satoru YANAGI, Kazuhiro ICHIKAWA, Satoru HOSONO, Jiro KATO, Tatsushi KATO, Shunichi SEKI
  • Patent number: 10661456
    Abstract: A force detection apparatus includes a first member, a second member placed to be opposed to the first member, a sensor device placed between the first member and the second member and including a force detection element having at a piezoelectric element that outputs a signal according to an external force, and a pressurization bolt provided in an outer periphery of the sensor device in a plan view as seen from a direction in which the first member and the second member overlap and pressurizing the sensor device, wherein the first member has a groove which is between the sensor device and the pressurization bolt in the plan view.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 26, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Shoichi Nagamatsu, Tatsushi Kato, Hiroki Kawai
  • Publication number: 20190001510
    Abstract: A force detection apparatus includes a first member, a second member placed to be opposed to the first member, a sensor device placed between the first member and the second member and including a force detection element having at a piezoelectric element that outputs a signal according to an external force, and a pressurization bolt provided in an outer periphery of the sensor device in a plan view as seen from a direction in which the first member and the second member overlap and pressurizing the sensor device, wherein the first member has a groove which is between the sensor device and the pressurization bolt in the plan view.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 3, 2019
    Inventors: Shoichi NAGAMATSU, Tatsushi KATO, Hiroki KAWAI
  • Patent number: 8985747
    Abstract: Provided is a piezoelectric element that has a first electrode, a piezoelectric layer provided on the first electrode, and a second electrode provided on the piezoelectric layer, an average grain size of crystal grains aligned in a planar direction within 15° from a (100) plane is less than the average grain size of the crystal grains facing a planar direction inclined by more than 15° from the (100) plane, in a case in which the crystal orientation of the piezoelectric layer is analyzed using an electron beam backscatter diffraction method (EBSD).
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: March 24, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Tomohiro Sakai, Tatsushi Kato
  • Publication number: 20150054888
    Abstract: Provided is a piezoelectric element that has a first electrode, a piezoelectric layer provided on the first electrode, and a second electrode provided on the piezoelectric layer, an average grain size of crystal grains aligned in a planar direction within 15° from a (100) plane is less than the average grain size of the crystal grains facing a planar direction inclined by more than 15° from the (100) plane, in a case in which the crystal orientation of the piezoelectric layer is analyzed using an electron beam backscatter diffraction method (EBSD).
    Type: Application
    Filed: August 20, 2014
    Publication date: February 26, 2015
    Inventors: Tomohiro SAKAI, Tatsushi KATO
  • Publication number: 20120038244
    Abstract: A method of manufacturing a piezoelectric vibration device having a surface acoustic wave element includes a step of forming a functional film adapted to increase a velocity of a wave on a surface of the surface acoustic wave element. Further, the Young's modulus of the functional film is higher than the Young's modulus of each of the excitation electrode and the piezoelectric body, and the density of the functional film is lower than the density of each of the excitation electrode and the piezoelectric body. Thus, it is possible to develop the frequency rise due to the elastic modulus rise while suppressing the influence of the frequency drop due to the mass attachment effect to thereby raise the resonant frequency of the surface acoustic wave element.
    Type: Application
    Filed: July 19, 2011
    Publication date: February 16, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsuhiro WADA, Tatsushi KATO, Satoru TANAKA
  • Patent number: 8035164
    Abstract: A semiconductor device includes: a substrate having a first surface; an insulation layer; a semiconductor layer disposed to the first surface of the substrate with the insulation layer interposed between the semiconductor layer and the first surface; and a piezoelectric layer that is positioned between the first surface and the semiconductor layer, and disposed in a region included and interposed in the insulation layer.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: October 11, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Tatsushi Kato
  • Patent number: 7525157
    Abstract: A semiconductor device includes: an insulating layer selectively formed on the semiconductor base material; a first semiconductor layer made of single-crystal and formed on the semiconductor base material that is exposed below the insulating layer, the first semiconductor layer having an opening that exposes the semiconductor base material; an opening plane exposing a side face of the first semiconductor layer and provided below the support film, the second semiconductor layer and the first semiconductor layer by using the mask pattern as a mask; a portion defining a hollow part between the second semiconductor layer and the semiconductor base material; a first insulating film formed in the hollow part; and a second insulating film formed above the semiconductor base material on which the first insulating film is formed.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 28, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Tatsushi Kato
  • Publication number: 20090101986
    Abstract: A semiconductor device includes: a substrate having a first surface; an insulation layer; a semiconductor layer disposed to the first surface of the substrate with the insulation layer interposed between the semiconductor layer and the first surface; and a piezoelectric layer that is positioned between the first surface and the semiconductor layer, and disposed in a region included and interposed in the insulation layer.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 23, 2009
    Applicant: Seiko Epson Corporation
    Inventor: Tatsushi KATO
  • Patent number: 7355248
    Abstract: A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the second insulating layer; a first gate electrode that is formed on the second semiconductor layer; first conductive-source and drain layers that are formed in the second semiconductor layer and are arranged at sides of the gate electrode; and a first wiring layer that connects the first gate electrode to the first semiconductor layer.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: April 8, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Tatsushi Kato
  • Publication number: 20070218617
    Abstract: A method of manufacturing a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate; forming a second semiconductor layer above the first semiconductor layer, the second semiconductor layer having a smaller selection ratio of wet-etching than the first semiconductor layer; forming a hole having the semiconductor substrate as a bottom face in a supporting member holding area by removing by etching the second semiconductor layer and the first semiconductor layer in the supporting member holding area; forming a supporting member film above the semiconductor substrate to fill in the hole and to cover the second semiconductor layer; forming a mask pattern above the supporting member film, the mask pattern covering a supporting member area and exposing another area; dry-etching the second semiconductor layer and the first semiconductor layer in sequence using the mask pattern as a mask to form a supporting member abutting on the semiconductor substrate at the bottom face of t
    Type: Application
    Filed: March 15, 2007
    Publication date: September 20, 2007
    Applicant: Seiko Epson Corporation
    Inventor: Tatsushi Kato
  • Publication number: 20070205462
    Abstract: A semiconductor device includes: a semiconductor base material; an insulating layer selectively formed on the semiconductor base material; a first semiconductor layer made of single-crystal and formed on the semiconductor base material that is exposed below the insulating layer, the first semiconductor layer having an opening that exposes the semiconductor base material; a second semiconductor layer made of a single-crystal whose wet-etching selectivity is smaller than a wet-etching selectivity of the first semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having the opening that exposes the semiconductor base material; a polycrystalline layer made of the same composition as the second semiconductor layer, the polycrystalline layer being formed on the insulating layer; a support film formed on a whole upper face of the semiconductor base material and filling the opening; a mask pattern formed on the support film so as to continuously cover at least a part of
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Applicant: Seiko Epson Corporation
    Inventor: Tatsushi Kato
  • Publication number: 20060118871
    Abstract: A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the second insulating layer; a first gate electrode that is formed on the second semiconductor layer; first conductive-source and drain layers that are formed in the second semiconductor layer and are arranged at sides of the gate electrode; and a first wiring layer that connects the first gate electrode to the first semiconductor layer.
    Type: Application
    Filed: November 14, 2005
    Publication date: June 8, 2006
    Applicant: Seiko Epson Corporation
    Inventor: Tatsushi Kato
  • Publication number: 20060118872
    Abstract: A semiconductor device includes: a semiconductor layer portion provided on an insulating layer, the semiconductor layer portion becoming an element formation region; a gate insulating layer provided on the semiconductor layer portion; a gate electrode provided on the gate insulating layer; and an impurity region provided in the semiconductor layer portion, the impurity region becoming a source or drain region. The semiconductor layer portion is provided with a recess and an isolation insulating layer formed by filling the recess with an insulating material.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 8, 2006
    Applicant: Seiko Epson Corporation
    Inventor: Tatsushi Kato