Abstract: An image processing apparatus receives input of an original image that is divided into at least two partial images in a top-and-bottom direction. The image processing apparatus adds a first line number of dummy screen lines to a top portion of a partial image that is a top portion of the original image. The image processing apparatus adds a second line number of dummy screen lines to a lower portion of a partial image that is a lower portion of the original image. The image processing apparatus uses a z×z encoding process unit and performs an encoding process for each of the partial images to which the dummy screen lines have been added.

Abstract: A moving image processing apparatus has an encoder unit configured to include a plurality of encoders which respectively encode a plurality of divided images into which images of a moving image are divided in such a manner that each divided image includes an overlapped area to generate encoded divided image data; and a decoder unit configured to include a plurality of decoders which respectively decode the plurality of encoded divided image data inputted from the encoder unit and respectively extract information on motion vectors of the divided images; and a composition unit which blends a plurality of decoded divided images decoded and generated by the plurality of decoders respectively in the overlapped area to output the images of the moving image. And the composition unit determines a blend ratio of the overlapped area based on the information on the motion vectors.

Abstract: A moving image processing apparatus has an encoder unit configured to include a plurality of encoders which respectively encode a plurality of divided images into which images of a moving image are divided in such a manner that each divided image includes an overlapped area to generate encoded divided image data; and a decoder unit configured to include a plurality of decoders which respectively decode the plurality of encoded divided image data inputted from the encoder unit and respectively extract information on motion vectors of the divided images; and a composition unit which blends a plurality of decoded divided images decoded and generated by the plurality of decoders respectively in the overlapped area to output the images of the moving image. And the composition unit determines a blend ratio of the overlapped area based on the information on the motion vectors.

Abstract: A transcoding device has been disclosed, which reduces the influence of an error even if the error has occurred in a decode image before re-encoding (transcoding). The transcoding device includes a decoder that decodes image data encoded in a first format and a transcoder that re-encodes image data supplied from the decoder into a second format, wherein the decoder calculates and outputs an amount of decode errors at the time of decoding and a transcoder 3 outputs re-encoded image data as it is or outputs it after replacement with skip data.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: A clocking circuit of a receiving unit performs a clocking operation synchronously with a network clock. A packet output circuit of the receiving unit outputs a second packet included in a first packet and outputs a control signal indicating normality/abnormality of output timing of the second packet based on a result of comparing a time of the clocking circuit and a time of first time information included in the first packet. A clock adjusting circuit of a processing unit synchronizes, when the second packet includes second time information indicating a time based on a transmitting side reference clock and when the control signal indicates normality, a receiving side reference clock with the transmitting side reference clock based on a result of comparing a time based on the receiving side reference clock and a time of the second time information.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: A semiconductor device includes an external pin, a control parameter decision circuit, and a register update circuit. The control parameter decision circuit includes a register and an output selector. The register is initialized in accordance with resetting of the semiconductor device. The output selector, according to a level value of an external input signal supplied via the external pin, selects one of a signal whose level value is set equal to a register value of the register and a signal whose level value is set opposite to the register value of the register, and outputs the selected signal as a control parameter signal. The register update circuit updates the register value of the register when a level value of the control parameter signal need be changed.

Abstract: An integrated circuit that enables a reduction in chip size and test time.

Abstract: A transcoding device has been disclosed, which reduces the influence of an error even if the error has occurred in a decode image before re-encoding (transcoding). The transcoding device includes a decoder that decodes image data encoded in a first format and a transcoder that re-encodes image data supplied from the decoder into a second format, wherein the decoder calculates and outputs an amount of decode errors at the time of decoding and a transcoder 3 outputs re-encoded image data as it is or outputs it after replacement with skip data.

Abstract: The invention provides a task scheduling method which can prevent overflowing of a buffer on a host system or a data encoding/decoding apparatus even when the transfer rate falls in case the compressed data and the non-compressed data are simultaneously transferred between the host system and the data encoding/decoding apparatus. In a task scheduling method, the compressed audio/video data is transferred from the buffer of the host system to an external device with a first transfer priority. The non-compressed audio/video data is transferred from the buffer to the external device with a second transfer priority lower than the first transfer priority.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: A video encoding device capable of performing a near-real-time encoding process while restraining deterioration in image quality. A first encoding section encodes a video signal to generate a first stream and extracts stream information including space- and time- related information of the video signal. A stream buffer stores video scenes of the first stream which correspond to a partial time of the video signal. An encoding control section analyzes a code generation rate and motion information from the stream information to generate encoding control information. A second encoding section encodes the first stream read from the stream buffer, in accordance with the encoding control information, to generate a second stream. The stream buffer stores multiples video scenes of the first stream by means of which a scene change can be detected as an information rate change.