Patents by Inventor Tatsushi Sano

Tatsushi Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8102743
    Abstract: A phase-locked loop circuit that generates a clock signal synchronized with an input signal with a predetermined frequency, including an oscillator configured to oscillate and generate the clock signal; a converter configured to convert the input signal into a digital signal using the clock signal generated by the oscillator as a sampling clock; a frequency divider configured to divide a frequency of the clock signal generated by the oscillator to generate a comparison clock signal and send the comparison clock signal as a feedback; a normalizer configured to normalize an amplitude value of the digital signal generated by the converter; and an oscillation controller configured to control a phase of the clock signal generated by the oscillator so as to reduce a phase difference between the normalized digital signal generated by the normalizer and the comparison clock signal sent as a feedback by the frequency divider.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: January 24, 2012
    Assignee: Sony Corporation
    Inventor: Tatsushi Sano
  • Patent number: 8065552
    Abstract: A clock generation circuit is provided that multiplies an input signal of a specific frequency by a specific multiplication factor and generates an output clock signal. The clock generation circuit includes a PLL circuit that multiplies the input signal and generates the output clock signal, and a correction circuit that changes the multiplication factor of the PLL circuit. The correction circuit changes the PLL circuit multiplication factor by increasing or decreasing the specific multiplication factor, the change being performed only during a correction interval for each correction cycle, the correction cycle being longer than one cycle of the input signal, and being performed such that a time difference between an input synchronizing signal synchronized with the input signal and an output synchronizing signal synchronized with the output clock signal is reduced. The PLL circuit multiplies the input signal by the changed multiplication factor during the correction interval.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: November 22, 2011
    Assignee: Sony Corporation
    Inventor: Tatsushi Sano
  • Patent number: 7496010
    Abstract: A push-pull signal is detected from light reflected from a disk-shaped storage medium on which wobbling grooves are formed as recording tracks and address information is recorded by forming pre-pits on lands between adjacent grooves. A fundamental amplitude variation signal indicating the fundamental amplitude variation of the push-pull signal is acquired, and a reference voltage is generated by adding an offset voltage to the fundamental amplitude variation signal. Pre-pits are detected by comparing the push-pull signal with the reference voltage. Because the reference voltage is produced on the basis of the fundamental amplitude variation signal indicating the variation components of the push-pull signal due to the wobbling of grooves and noise, the variation components due to the wobbling and noise are reflected in the reference voltage. Furthermore, the variation components of the push-pull signal corresponding to the pre-pits are also reflected to a properly small extent in the reference voltage.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: February 24, 2009
    Assignee: Sony Corporation
    Inventors: Shinji Ohta, Tatsushi Sano
  • Publication number: 20090028017
    Abstract: A phase-locked loop circuit that generates a clock signal synchronized with an input signal with a predetermined frequency, including an oscillator configured to oscillate and generate the clock signal; a converter configured to convert the input signal into a digital signal using the clock signal generated by the oscillator as a sampling clock; a frequency divider configured to divide a frequency of the clock signal generated by the oscillator to generate a comparison clock signal and send the comparison clock signal as a feedback; a normalizer configured to normalize an amplitude value of the digital signal generated by the converter; and an oscillation controller configured to control a phase of the clock signal generated by the oscillator so as to reduce a phase difference between the normalized digital signal generated by the normalizer and the comparison clock signal sent as a feedback by the frequency divider.
    Type: Application
    Filed: June 20, 2008
    Publication date: January 29, 2009
    Applicant: Sony Corporation
    Inventor: Tatsushi SANO
  • Publication number: 20090009222
    Abstract: A clock generation circuit is provided that multiplies an input signal of a specific frequency by a specific multiplication factor and generates an output clock signal. The clock generation circuit includes a PLL circuit that multiplies the input signal and generates the output clock signal, and a correction circuit that changes the multiplication factor of the PLL circuit. The correction circuit changes the PLL circuit multiplication factor by increasing or decreasing the specific multiplication factor, the change being performed only during a correction interval for each correction cycle, the correction cycle being longer than one cycle of the input signal, and being performed such that a time difference between an input synchronizing signal synchronized with the input signal and an output synchronizing signal synchronized with the output clock signal is reduced. The PLL circuit multiplies the input signal by the changed multiplication factor during the correction interval.
    Type: Application
    Filed: May 27, 2008
    Publication date: January 8, 2009
    Applicant: Sony Corporation
    Inventor: Tatsushi Sano
  • Patent number: 7437649
    Abstract: Data is arranged to one block obtained after a CIRC process so that a predetermined data pattern is recorded into a predetermined portion on a disc. By tracing back an encoding step of a Cross-Interleave Reed-Solomon Code (CIRC), a layout of recording data of one block before the CIRC process for allowing the predetermined data pattern to be recorded into the predetermined portion is obtained. An error correcting process of a CD-ROM mode 1 is executed. If a position of a parity coincides with data for forming the predetermined data pattern, a value of user data of an encoding sequence to form the parity is changed. After error correction encoding of a CD-ROM is executed, encoding of the CIRC is executed to the recording data of one block.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: October 14, 2008
    Assignee: Sony Corporation
    Inventors: Akiya Saito, Toru Aida, Yoriaki Kanada, Tatsushi Sano, Toshihiko Senno, Yoshinobu Usui, Yoichiro Sako, Tatsuya Inokuchi, Shunsuke Furukawa, Yoshiro Miyoshi, Takashi Kihara
  • Patent number: 7333408
    Abstract: In a demodulation process of a first modulated signal and a second modulated signal, phase adjustment is automatically performed by generating, in response to demodulation results, an optimum phase value of a second internal reference wave for demodulating the second modulated signal. A phase of a second internal reference wave for demodulating the first modulated signal is also adjusted using the optimum phase value for the automatic adjustment.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: February 19, 2008
    Assignee: Sony Corporation
    Inventors: Tatsushi Sano, Mitsuru Okabe, Tadaaki Nomoto
  • Patent number: 7304923
    Abstract: A push pull signal is detected from a disk-shaped storage medium on which wobbling grooves are formed as recording tracks and address information is recorded by forming pre-pits on lands between adjacent grooves. The detected push-pull signal is compared with a reference voltage thereby generating a land pre-pit detection signal. Of pulses included in the land pre-pit detection signal, those pulses having a small pulse width are regarded as noise pulses and removed thereby obtaining a corrected land pre-pit detection signal. The number of pulses included in the land pre-pit detection signal is counted, and the reference voltage is controlled in accordance with the counted number of pulses.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: December 4, 2007
    Assignee: Sony Corporation
    Inventors: Tatsushi Sano, Mitsuyuki Bamba, Toshimasa Miyoshi
  • Patent number: 7304932
    Abstract: A recording method for converting m-bit data into n-bit (where n>m) bit data whose run length is restricted and recoding the converted data on a recording medium, the recording method comprising the steps of when at least preceded data is data containing a special data pattern, lightening the restriction of the run length; and recording data so that the cumulative value of DC components per unit time increase when the data is reproduced in the state that the run length is restricted.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: December 4, 2007
    Assignees: Sony Corporation, Sony Disc & Digital Solutions Inc.
    Inventors: Yoichiro Sako, Tatsuya Inokuchi, Takashi Kihara, Shunsuke Furukawa, Yoriaki Kanada, Akiya Saito, Toru Aida, Tatsushi Sano, Yoshiro Miyoshi, Yoshinobu Usui, Toshihiko Senno
  • Patent number: 7289046
    Abstract: A recording method for converting m-bit data into n-bit (where n>m) data whose run length is restricted and recording the converted data on a recording medium, the recording method comprising the step of selecting first n-bit data according to an immediately preceded n-bit data, first n-bit data immediately followed thereby, and second n-bit data immediately followed thereby so that the cumulative value of DC components per unit time becomes small.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: October 30, 2007
    Assignees: Sony Corporation, Sony Disc & Digital Solutions Inc.
    Inventors: Yoichiro Sako, Toru Aida, Tatsuya Inokuchi, Akiya Saito, Takashi Kihara, Tatsushi Sano, Yoriaki Kanada, Yoshiro Miyoshi, Shunsuke Furukawa, Yoshinobu Usui, Toshihiko Senno
  • Patent number: 7272098
    Abstract: A recording method includes the steps of generating recording data in such a manner that, when m-bit data is converted into a data symbol of n bits (m<n), and connection bits such that the summed value of DC components per unit time decreases are selected from among a plurality of connection bits and are added after the m-bit data symbol, the connection bits differing from connection bits which are added when the n-bit data symbol is a data symbol other than the special data symbol are added to generate recording data; and recording the generated recording data on a recording medium.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: September 18, 2007
    Assignees: Sony Corporation, Sony Disc & Digital Solutions Inc.
    Inventors: Yoichiro Sako, Tatsuya Inokuchi, Shunsuke Furukawa, Takashi Kihara, Toru Aida, Akiya Saito, Yoriaki Kanada, Tatsushi Sano, Yoshiro Miyoshi, Toshihiko Senno, Yoshinobu Usui
  • Patent number: 7233267
    Abstract: A recording method, wherein, when a certain portion of main data is recorded by being encoded by a first encoding method and the other portions of the main data is recorded by being encoded by a second encoding method, an encoding process is performed by the first encoding method so that, when data which is recorded in such a manner that the data encoded by the first encoding method is decoded by a decoding method corresponding to the first encoding method, and thereafter, is further encoded by the second encoding method, is decoded by a decoding method corresponding to the second encoding method, the sum value of DC components per unit time increases.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: June 19, 2007
    Assignees: Sony Corporation, Sony Disc & Digital Solutions Inc.
    Inventors: Yoichiro Sako, Tatsuya Inokuchi, Takashi Kihara, Shunsuke Furukawa, Yoriaki Kanada, Akiya Saito, Toru Aida, Tatsushi Sano, Toshihiko Senno, Yoshinobu Usui
  • Patent number: 7215260
    Abstract: Six record areas for predetermined data that has been encoded and digitally modulated are formed in a data record area on a disc. The record areas have different offset compensation amounts. The offset compensation amounts allow all offset amounts that may take place in an error correction code encoder to be compensated. Thus, regardless of the offset amount generated by the error correction code encoder, encoded and modulated data that has been generated by the conventional EFM modulating system and recorded in one of the record areas securely causes DSV to deviate. Each of the record areas is set to a sufficient length that allows the effect of which DSV deviates to be recognized.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 8, 2007
    Assignee: Sony Corporation
    Inventors: Toru Aida, Yoichiro Sako, Tatsuya Inokuchi, Akiya Saito, Takashi Kihara, Tatsushi Sano, Yoriaki Kanada, Yoshiro Miyoshi, Shunsuke Furukawa, Yoshinobu Usui, Toshihiko Senno
  • Patent number: 7203141
    Abstract: A recording medium has a first area in which data encoded with a first error correction code is recorded and a second area in which data encoded with the first error correction code and data decodable with a second error correction code that is different from the first error correction code are mixedly recorded. Data that causes the cumulated value of a DC component per unit period of data reproduced from the second area to deviate is recorded in the second area.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: April 10, 2007
    Assignees: Sony Corporation, Sony Disc & Digital Solutions Inc.
    Inventors: Tatsuya Inokuchi, Yoichiro Sako, Takashi Kihara, Shunsuke Furukawa, Yoriaki Kanada, Akiya Saito, Toru Aida, Tatsushi Sano, Toshihiko Senno, Yoshinobu Usui
  • Patent number: 7167438
    Abstract: The S/N ratio is improved for recording data to grooves (2-1,2-2) of an optical disc so that as much information as possible can be recorded at the lowest possible frequency band. An optical disc using wobble patterns to record different information has a first groove (2-1) having a first wobble pattern (22) in which one wobble period has a sharp rising edge and a gradual falling edge; and a second groove (2-2) having a second wobble pattern (24) in which one wobble period has a gradual rising edge and a sharp falling edge. Each of the first and the second wobble pattern is represented by a first fundamental and a second harmonic of a Fourier series. The polarity of the second harmonic, which is an even harmonic, of the second wobble pattern is opposite that of the first wobble pattern. A method for manufacturing this optical disc is also provided.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: January 23, 2007
    Assignees: Matsushita Electric Industrial Co., Ltd., Koninklijke Philips Electronics N.V., Sony Corporation
    Inventors: Jacobus Petrus Josephus Heemskerk, Cornelis Marinus Schep, Aalbert Stek, Shigeru Furumiya, Hiromichi Ishibashi, Junichi Minamino, Hiroshi Ogawa, Shin Masuhara, Tatsushi Sano
  • Publication number: 20060202869
    Abstract: Six record areas for predetermined data that has been encoded and digitally modulated are formed in a data record area on a disc. The record areas have different offset compensation amounts. The offset compensation amounts allow all offset amounts that may take place in an error correction code encoder to be compensated. Thus, regardless of the offset amount generated by the error correction code encoder, encoded and modulated data that has been generated by the conventional EFM modulating system and recorded in one of the record areas securely causes DSV to deviate. Each of the record areas is set to a sufficient length that allows the effect of which DSV deviates to be recognized.
    Type: Application
    Filed: June 27, 2003
    Publication date: September 14, 2006
    Applicant: Sony Corporation
    Inventors: Toru Aida, Yoichiro Sako, Tatsuya Inokuchi, Akiya Saito, Takashi Kihara, Tatsushi Sano, Yoriaki Kanada, Yoshiro Miyoshi, Shunsuke Furukawa, Yoshinobu Usui, Toshihiko Senno
  • Publication number: 20050226132
    Abstract: A recording medium has a first area in which data encoded with a first error correction code is recorded and a second area in which data encoded with the first error correction code and data decodable with a second error correction code that is different from the first error correction code are mixedly recorded. Data that causes the cumulated value of a DC component per unit period of data reproduced from the second area to deviate is recorded in the second area.
    Type: Application
    Filed: May 20, 2003
    Publication date: October 13, 2005
    Applicants: Sony Corporation, Sony Disc Technology Inc.
    Inventors: Tatsuya Inokuchi, Yoichiro Sako, Takashi Kihara, Shunsuke Furukawa, Yoriaki Kanada, Akiya Saito, Toru Aida, Tatsushi Sano, Toshihiko Senno, Yoshinobu Usui
  • Publication number: 20050195511
    Abstract: In a demodulation process of a first modulated signal and a second modulated signal, phase adjustment is automatically performed by generating, in response to demodulation results, an optimum phase value of a second internal reference wave for demodulating the second modulated signal. A phase of a second internal reference wave for demodulating the first modulated signal is also adjusted using the optimum phase value for the automatic adjustment.
    Type: Application
    Filed: January 31, 2005
    Publication date: September 8, 2005
    Applicant: Sony Corporation
    Inventors: Tatsushi Sano, Mitsuru Okabe, Tadaaki Nomoto
  • Publication number: 20050086578
    Abstract: Data is arranged to one block obtained after a CIRC process so that a predetermined data pattern is recorded into a predetermined portion on a disc. By tracing back an encoding step of a CIRC, a layout of recording data of one block before the CIRC process for allowing the predetermined data pattern to be recorded into the predetermined portion is obtained. An error correcting process of a CD-ROM mode 1 is executed. If a position of a parity coincides with data for forming the predetermined data pattern, a value of user data of an encoding sequence to form the parity is changed. After error correction encoding of a CD-ROM is executed, encoding of the CIRC is executed to the recording data of one block.
    Type: Application
    Filed: July 16, 2003
    Publication date: April 21, 2005
    Applicant: Sony Corporation
    Inventors: Akiya Saito, Toru Aida, Yoriaki Kanada, Tatsushi Sano, Toshihiko Senno, Yoshinobu Usui, Yoichiro Sako, Tatsuya Inokuchi, Shunsuke Furukawa, Yoshiro Miyoshi, Takashi Kihara
  • Publication number: 20050058056
    Abstract: The S/N ratio is improved for recording data to grooves (2-1,2-2) of an optical disc so that as much information as possible can be recorded at the lowest possible frequency band. An optical disc using wobble patterns to record different information has a first groove (2-1) having a first wobble pattern (22) in which one wobble period has a sharp rising edge and a gradual falling edge; and a second groove (2-2) having a second wobble pattern (24) in which one wobble period has a gradual rising edge and a sharp falling edge. Each of the first and the second wobble pattern is represented by a first fundamental and a second harmonic of a Fourier series. The polarity of the second harmonic, which is an even harmonic, of the second wobble pattern is opposite that of the first wobble pattern. A method for manufacturing this optical disc is also provided.
    Type: Application
    Filed: October 16, 2002
    Publication date: March 17, 2005
    Inventors: Jacobus Heemskerk, Cornelis Schep, Aalbert Stek, Shigeru Furumiya, Hiromichi Ishibashi, Junichi Minamino, Hiroshi Ogawa, Shin Masuhara, Tatsushi Sano