Patents by Inventor Tatsuya Fukumura

Tatsuya Fukumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210003918
    Abstract: A resist composition containing a polymer compound having a constitutional unit (a01) represented by Formula (a01), and a fluororesin component having a constitutional unit (f10) represented by Formula (f1-01) or (f1-02), in which the constitutional unit (a01) is a constitutional unit which contains a specific acid dissociable group (a01-r-1) containing an aliphatic cyclic group and an aromatic cyclic group; in Formulae (f1-01) and (f1-02), R represents a hydrogen atom, at least one of Raf01 and Raf02 and at least one of Raf03 and Raf04 represent a hydrocarbon group substituted with a fluorine atom, and the total number of fluorine atoms is 3 or greater.
    Type: Application
    Filed: June 2, 2020
    Publication date: January 7, 2021
    Inventors: Yuki FUKUMURA, Tasuku MATSUMIYA, Tatsuya FUJII
  • Publication number: 20200409262
    Abstract: A resist composition including a base component and a fluorine additive component (F), the component (F) including a copolymer having a structural unit (f1) represented by general formula (f1-1) or (f1-2), and a structural unit (f2) represented by general formula (f2-1) (in formula (f1-1) and (f2-1), R represents a hydrogen atom or the like; at least one of Raf11 and Raf12, and at least one of Raf13 and Raf14 represents a hydrocarbon group substituted with a fluorine atom, and the total number of carbon atoms is 3 or more, provided that a hydrocarbon group forming a bridge structure is excluded; and the structural unit (f2) has a specific acid dissociable group containing an aliphatic cyclic group having no bridge structure
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Inventors: Yuki FUKUMURA, Tatsuya FUJII, Yoichi HORI
  • Publication number: 20200159119
    Abstract: A resist composition including a structural unit represented by General Formula (a0-1), a structural unit containing a cyclic group in which —O—C(?O)— forms a part of a ring skeleton (excluding a cyclic group forming a cross-linked structure), and a structural unit represented by General Formula (a0-3); in the General Formula (a0-1), Rx01 is an acid dissociable group represented by General Formula (a01-r-1) or General Formula (a01-r-2); in the Formula (a01-r-1) and Formula (a01-r-2), Xa and Ya, and Xaa and Yaa are groups that together form an aliphatic cyclic group that does not have a cross-linked structure; in General Formula (a0-3), Yax3 is a single bond or an (nax3+1)-valent linking group.
    Type: Application
    Filed: November 8, 2019
    Publication date: May 21, 2020
    Inventors: Tatsuya FUJII, Yuki FUKUMURA
  • Publication number: 20200159118
    Abstract: A resist composition including a structural unit represented by General Formula (a0-1), a structural unit represented by General Formula (a0-2), and a structural unit represented by General Formula (a0-3); in the Formula (a0-1), Rx01 is an acid dissociable group represented by General Formula (a01-r-1) or General Formula (a01-r-2) in Formula (a01-r-1) and Formula (a01-r-2), Xa and Ya, and Xaa and Yaa are groups that together form an aliphatic cyclic group having 3 to 5 carbon atoms; in Formula (a0-2), R1 is a fluorinated alkyl group; in Formula (a0-3), Wax3 is an aromatic hydrocarbon group.
    Type: Application
    Filed: November 8, 2019
    Publication date: May 21, 2020
    Inventors: Tatsuya FUJII, Yuki FUKUMURA, Masahito YAHAGI, Yoichi HORI
  • Publication number: 20200142303
    Abstract: A resist composition including a polymeric compound having a structural unit in which a compound represented by formula (a0-1) has a polymerizable group within the W1 portion converted into a main chain, and a compound represented by formula (b1-1) in which W1 represents a polymerizable group-containing group; Ct represents a tertiary carbon atom, and the ?-position of Ct is a carbon atom which constitutes a carbon-carbon unsaturated bond; R11 represents an aromatic hydrocarbon group or a chain hydrocarbon group; R12 and R13 are mutually bonded to form a 5-membered aliphatic monocyclic group, or a condensed polycyclic hydrocarbon group containing a 5-membered aliphatic monocyclic ring; Rb11 represents a cyclic group; Rb10, Rb20 and Rb30 each independently represents a substituent; nb1 represents an integer of 0 to 4; nb2 represents an integer of 0 to 5; nb3 represents an integer of 0 to 5; and X? represents a counteranion.
    Type: Application
    Filed: October 14, 2019
    Publication date: May 7, 2020
    Inventors: Masahito YAHAGI, Yoichi HORI, Tatsuya FUJII, Yuki FUKUMURA
  • Patent number: 10394122
    Abstract: A resist composition which generates an acid upon exposure and changes a solubility in a developing solution under an action of the acid, the resist composition containing a base material component whose solubility in the developing solution changes under the action of an acid and an acid generator represented by general formula (b1). In general formula (b-1), Rb1 represents an aromatic hydrocarbon group having at least one alkyl group having 3 or more carbon atoms as a substituent, Yb1 represents a divalent linking group containing an ester bond (—C(?O)—O— or —O—C(?O)—), Vb1 represents an alkylene group, a fluorinated alkylene group, or a single bond, m is an integer of 1 or more, and Mm+ represents an m-valent organic cation.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: August 27, 2019
    Assignee: TOYKO OHKA KOGYO CO., LTD.
    Inventors: Issei Suzuki, Masahito Yahagi, Yuki Fukumura, Kazuaki Ebisawa, Yoshitaka Komuro, Toshikazu Takayama, Takashi Kamizono, Tatsuya Fujii
  • Publication number: 20190219920
    Abstract: A resist composition which generates acid upon exposure and exhibits changed solubility in a developing solution under action of acid, and which includes a polymeric compound having a structural unit represented by general formula (a0-1) (wherein R represents a hydrogen atom, an alkyl group of 1 to 5 carbon atoms or a halogenated alkyl group of 1 to 5 carbon atoms; Va0 represents a divalent hydrocarbon group; na0 represents an integer of 0 to 2; Ra00 represents an acid dissociable group represented by general formula (a0-r1-1); Ra01 and Ra02 represents a hydrocarbon group; Ra01 and Ra02 may be mutually bonded to form a ring; Ya0 represents a quaternary carbon atom; Ra031, Ra032 and Ra033 each independently represents a hydrocarbon group, provided that at least one of Ra031, Ra032 and Ra033 is a hydrocarbon group having a polar group).
    Type: Application
    Filed: October 4, 2017
    Publication date: July 18, 2019
    Inventors: Takashi NAGAMINE, Hideto NITO, Masafumi FUJISAKI, Tatsuya FUJII, Yuki FUKUMURA, Takahiro KOJIMA, Issei SUZUKI, Takuya IKEDA, KhanhTin NGUYEN
  • Patent number: 10147738
    Abstract: According to one embodiment, a first semiconductor body extends in a stacking direction of a stacked body through a first stacked unit and contacts a foundation layer. A plurality of contact vias extend in the stacking direction through an insulating layer and contact a plurality of terrace portions. A second semiconductor body extends in the stacking direction through a second stacked unit. An insulating film is provided between the foundation layer and a lower end portion of the second semiconductor body.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tatsuya Fukumura
  • Publication number: 20170236834
    Abstract: According to one embodiment, a first semiconductor body extends in a stacking direction of a stacked body through a first stacked unit and contacts a foundation layer. A plurality of contact vias extend in the stacking direction through an insulating layer and contact a plurality of terrace portions. A second semiconductor body extends in the stacking direction through a second stacked unit. An insulating film is provided between the foundation layer and a lower end portion of the second semiconductor body.
    Type: Application
    Filed: July 12, 2016
    Publication date: August 17, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tatsuya FUKUMURA
  • Patent number: 9666239
    Abstract: According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: May 30, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Naito, Tatsuya Fukumura
  • Patent number: 9412747
    Abstract: A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 9, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Fukumura, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
  • Patent number: 9391178
    Abstract: Provided is a method of manufacturing a semiconductor device which allows an operation of the semiconductor device to be stabilized without increasing the area occupied thereby. The control gate electrode of a memory cell transistor is formed, and then the memory gate electrode thereof is formed on a lateral side of the control gate electrode. Then, memory offset spacers are formed over the side walls of the memory gate electrode. Then, the memory source region of the memory cell transistor is formed by ion implantation using the memory gate electrode, the memory offset spacers, and the like as a mask. Then, the memory drain region of the memory cell transistor is formed by ion implantation. Then, in the memory cell transistor, sidewall insulating films are formed. The memory offset spacers disappear through cleaning or the like before the sidewall insulating films are formed.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: July 12, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuya Fukumura
  • Publication number: 20160064399
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral circuit region arranged on a semiconductor substrate. In the peripheral circuit region, a stacked body including a tunnel insulating film, a floating gate electrode film, an inter-electrode insulating film, and a control gate electrode film stacked in this order, a first insulating film and a second insulating film are stacked on the semiconductor substrate. The peripheral circuit region includes a contact region where the stacked body removed a film above the floating gate electrode film, the first insulating film and the second insulating film are stacked. The peripheral circuit region includes contact provided within a region where the contact region is formed, and one end of the contact is in the second insulating film, and the other end of the contact is in the floating gate electrode film.
    Type: Application
    Filed: December 12, 2014
    Publication date: March 3, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki NAITO, Tatsuya FUKUMURA
  • Publication number: 20160035396
    Abstract: According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance.
    Type: Application
    Filed: March 2, 2015
    Publication date: February 4, 2016
    Inventors: Hiroaki NAITO, Tatsuya FUKUMURA
  • Publication number: 20150372079
    Abstract: According to an embodiment, a non-volatile semiconductor memory device includes plural gate electrodes in which a first insulating film, a charge storage layer, a second insulating film, and a control gate electrode layer are sequentially stacked on a semiconductor substrate, in which the control gate electrode layer includes a polysilicon layer that is formed on the second insulating film and a metal layer that is formed on the polysilicon layer, and a portion of the metal layer having the maximum width dimension is positioned above a lower end portion of the metal layer.
    Type: Application
    Filed: February 17, 2015
    Publication date: December 24, 2015
    Inventors: Hiroaki NAITO, Tatsuya FUKUMURA
  • Publication number: 20150129947
    Abstract: A nonvolatile semiconductor storage device includes a NAND string including memory cells disposed in a first direction and a select gate disposed first-directionally adjacent to a first memory cell located at an end of the memory cells. A first gap is disposed between the memory cells and a second gap is disposed between the first memory cell and the select gate. Further, in a cross sectional shape, an upper end of the second gap is higher than an upper end of a first gap and an upper portion of the second gap is curved.
    Type: Application
    Filed: February 24, 2014
    Publication date: May 14, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi NAGASHIMA, Hideyuki YAMAWAKI, Tatsuhiro ODA, Tatsuya FUKUMURA
  • Publication number: 20150072514
    Abstract: A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 12, 2015
    Inventors: Tatsuya FUKUMURA, Yoshihiro IKEDA, Shunichi NARUMI, Izumi TAKESUE
  • Patent number: 8907399
    Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Fukumura, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
  • Publication number: 20130307048
    Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
    Type: Application
    Filed: May 28, 2013
    Publication date: November 21, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Tatsuya FUKUMURA, Yoshihiro IKEDA, Shunichi NARUMI, Izumi TAKESUE
  • Patent number: 8546151
    Abstract: Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Haruo Furuta, Shuichi Ueno, Ryoji Matsuda, Tatsuya Fukumura, Takeharu Kuroiwa, Lien-Chang Wang, Eugene Chen, Yiming Huai