Patents by Inventor Tatsuya Fukumura
Tatsuya Fukumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10147738Abstract: According to one embodiment, a first semiconductor body extends in a stacking direction of a stacked body through a first stacked unit and contacts a foundation layer. A plurality of contact vias extend in the stacking direction through an insulating layer and contact a plurality of terrace portions. A second semiconductor body extends in the stacking direction through a second stacked unit. An insulating film is provided between the foundation layer and a lower end portion of the second semiconductor body.Type: GrantFiled: July 12, 2016Date of Patent: December 4, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Tatsuya Fukumura
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Publication number: 20170236834Abstract: According to one embodiment, a first semiconductor body extends in a stacking direction of a stacked body through a first stacked unit and contacts a foundation layer. A plurality of contact vias extend in the stacking direction through an insulating layer and contact a plurality of terrace portions. A second semiconductor body extends in the stacking direction through a second stacked unit. An insulating film is provided between the foundation layer and a lower end portion of the second semiconductor body.Type: ApplicationFiled: July 12, 2016Publication date: August 17, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Tatsuya FUKUMURA
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Patent number: 9666239Abstract: According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance.Type: GrantFiled: March 2, 2015Date of Patent: May 30, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hiroaki Naito, Tatsuya Fukumura
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Patent number: 9412747Abstract: A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates.Type: GrantFiled: November 19, 2014Date of Patent: August 9, 2016Assignee: Renesas Electronics CorporationInventors: Tatsuya Fukumura, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
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Patent number: 9391178Abstract: Provided is a method of manufacturing a semiconductor device which allows an operation of the semiconductor device to be stabilized without increasing the area occupied thereby. The control gate electrode of a memory cell transistor is formed, and then the memory gate electrode thereof is formed on a lateral side of the control gate electrode. Then, memory offset spacers are formed over the side walls of the memory gate electrode. Then, the memory source region of the memory cell transistor is formed by ion implantation using the memory gate electrode, the memory offset spacers, and the like as a mask. Then, the memory drain region of the memory cell transistor is formed by ion implantation. Then, in the memory cell transistor, sidewall insulating films are formed. The memory offset spacers disappear through cleaning or the like before the sidewall insulating films are formed.Type: GrantFiled: March 21, 2013Date of Patent: July 12, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuya Fukumura
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Publication number: 20160064399Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral circuit region arranged on a semiconductor substrate. In the peripheral circuit region, a stacked body including a tunnel insulating film, a floating gate electrode film, an inter-electrode insulating film, and a control gate electrode film stacked in this order, a first insulating film and a second insulating film are stacked on the semiconductor substrate. The peripheral circuit region includes a contact region where the stacked body removed a film above the floating gate electrode film, the first insulating film and the second insulating film are stacked. The peripheral circuit region includes contact provided within a region where the contact region is formed, and one end of the contact is in the second insulating film, and the other end of the contact is in the floating gate electrode film.Type: ApplicationFiled: December 12, 2014Publication date: March 3, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hiroaki NAITO, Tatsuya FUKUMURA
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Publication number: 20160035396Abstract: According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance.Type: ApplicationFiled: March 2, 2015Publication date: February 4, 2016Inventors: Hiroaki NAITO, Tatsuya FUKUMURA
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Publication number: 20150372079Abstract: According to an embodiment, a non-volatile semiconductor memory device includes plural gate electrodes in which a first insulating film, a charge storage layer, a second insulating film, and a control gate electrode layer are sequentially stacked on a semiconductor substrate, in which the control gate electrode layer includes a polysilicon layer that is formed on the second insulating film and a metal layer that is formed on the polysilicon layer, and a portion of the metal layer having the maximum width dimension is positioned above a lower end portion of the metal layer.Type: ApplicationFiled: February 17, 2015Publication date: December 24, 2015Inventors: Hiroaki NAITO, Tatsuya FUKUMURA
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Publication number: 20150129947Abstract: A nonvolatile semiconductor storage device includes a NAND string including memory cells disposed in a first direction and a select gate disposed first-directionally adjacent to a first memory cell located at an end of the memory cells. A first gap is disposed between the memory cells and a second gap is disposed between the first memory cell and the select gate. Further, in a cross sectional shape, an upper end of the second gap is higher than an upper end of a first gap and an upper portion of the second gap is curved.Type: ApplicationFiled: February 24, 2014Publication date: May 14, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi NAGASHIMA, Hideyuki YAMAWAKI, Tatsuhiro ODA, Tatsuya FUKUMURA
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Publication number: 20150072514Abstract: A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates.Type: ApplicationFiled: November 19, 2014Publication date: March 12, 2015Inventors: Tatsuya FUKUMURA, Yoshihiro IKEDA, Shunichi NARUMI, Izumi TAKESUE
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Patent number: 8907399Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.Type: GrantFiled: May 28, 2013Date of Patent: December 9, 2014Assignee: Renesas Electronics CorporationInventors: Tatsuya Fukumura, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
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Publication number: 20130307048Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.Type: ApplicationFiled: May 28, 2013Publication date: November 21, 2013Applicant: Renesas Electronics CorporationInventors: Tatsuya FUKUMURA, Yoshihiro IKEDA, Shunichi NARUMI, Izumi TAKESUE
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Patent number: 8546151Abstract: Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode.Type: GrantFiled: February 25, 2008Date of Patent: October 1, 2013Assignee: Renesas Electronics CorporationInventors: Haruo Furuta, Shuichi Ueno, Ryoji Matsuda, Tatsuya Fukumura, Takeharu Kuroiwa, Lien-Chang Wang, Eugene Chen, Yiming Huai
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Publication number: 20130253690Abstract: Provided is a method of manufacturing a semiconductor device which allows an operation of the semiconductor device to be stabilized without increasing the area occupied thereby. The control gate electrode of a memory cell transistor is formed, and then the memory gate electrode thereof is formed on a lateral side of the control gate electrode. Then, memory offset spacers are formed over the side walls of the memory gate electrode. Then, the memory source region of the memory cell transistor is formed by ion implantation using the memory gate electrode, the memory offset spacers, and the like as a mask. Then, the memory drain region of the memory cell transistor is formed by ion implantation. Then, in the memory cell transistor, sidewall insulating films are formed. The memory offset spacers disappear through cleaning or the like before the sidewall insulating films are formed.Type: ApplicationFiled: March 21, 2013Publication date: September 26, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuya FUKUMURA
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Publication number: 20130203187Abstract: The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode.Type: ApplicationFiled: March 14, 2013Publication date: August 8, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masamichi MATSUOKA, Tatsuya FUKUMURA
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Patent number: 8466507Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.Type: GrantFiled: August 1, 2011Date of Patent: June 18, 2013Assignee: Renesas Electronics CorporationInventors: Tatsuya Fukumura, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
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Patent number: 8212305Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.Type: GrantFiled: December 9, 2009Date of Patent: July 3, 2012Assignee: Renesas Electronics CorporationInventors: Tatsuya Fukumura, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
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Publication number: 20120068282Abstract: To provide a semiconductor device capable of suppressing a short circuit between an upper conductive element and a lower conductive element which constitute an MRAM, and a manufacturing method of the same. There are provided a semiconductor substrate having a main surface, a magnetic tunnel junction structure located over the main surface of the semiconductor substrate and including a pin layer, a tunnel insulating layer, and a free layer, a lower insulating layer contacting a lower side surface of the magnetic tunnel junction structure, a sidewall insulating layer located over the lower insulating layer in contact with the upper side surface of the magnetic tunnel junction structure, and exposing the top surface of the magnetic tunnel junction structure, and a conductive layer contacting the top surface of the magnetic tunnel junction structure exposed from the sidewall insulating layer.Type: ApplicationFiled: July 22, 2011Publication date: March 22, 2012Inventors: Masamichi MATSUOKA, Tatsuya Fukumura, Fumihiko Nitta
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Publication number: 20110284945Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.Type: ApplicationFiled: August 1, 2011Publication date: November 24, 2011Inventors: Tatsuya FUKUMURA, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
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Publication number: 20110198715Abstract: The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode.Type: ApplicationFiled: February 8, 2011Publication date: August 18, 2011Inventors: Masamichi MATSUOKA, Tatsuya Fukumura