Patents by Inventor Tatsuya Hirose

Tatsuya Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11098628
    Abstract: A clogging determination device includes a first antenna disposed at one of a side of a first end and a side of a second end of a filter disposed internally of a case, a second antenna disposed at the other of the side of the first end and the side of the second end of the filter, a multi-tone signal generator that has an output terminal coupled to the first antenna, outputs from the output terminal a multi-tone signal obtained by compositing a plurality of signals having different frequencies, and moves a position of an envelope of the multi-tone signal emitted to the filter from the first antenna, a detector that is coupled to the second antenna, and detects an intensity of the multi-tone signal received by the second antenna, and a determinator that determines a degree of clogging of the filter based on an intensity of the multi-tone signal.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 24, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10763737
    Abstract: A waveform shaping circuit includes a first variable gate voltage circuit that controls a minimum voltage of a pulse voltage based on a drain current or a source current of a field effect transistor, the pulse voltage having a positive or negative value and being applied to a gate of the field effect transistor, and a second variable gate voltage circuit that controls a maximum voltage of the pulse voltage based on the drain current or the source current.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 1, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10746076
    Abstract: A particulate matter detection circuit includes, a negative resistance circuit that couples to a first antenna inserted in a housing accommodating a first filter that filters an exhaust gas, couples to a second antenna inserted in the housing via a matching circuit that performs an impedance matching and a second filter that narrows the frequency band of a passing signal, and oscillates at a resonance frequency of the housing, and a detection circuit that outputs a voltage value corresponding to a signal strength of a radio wave received by a third antenna or the second antenna inserted in the housing. The resonance frequency of the housing varies depending on an amount of matter adhered to the first filter.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10734907
    Abstract: Based on a control voltage outputted by a secondary-side control circuit and a drain voltage of a second transistor that has a drain electrode connected to a primary winding of a transformer and performs switching operations based on a gate voltage, a control voltage generating circuit of a synchronous rectifier circuit generates the gate voltage of a first transistor. The gate voltage turns off the first transistor irrespective of the control voltage at timing where the drain voltage falls from a first value to a second value.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 4, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10715026
    Abstract: A gate driving circuit includes a first transistor, a first control circuit that changes a gate voltage of the first transistor from a low level to a high level, and a second control circuit that changes the gate voltage of the first transistor from the high level to the low level, wherein the first control circuit and the second control circuit are coupled to each other in parallel with respect to a gate of the first transistor.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: July 14, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10631446
    Abstract: An electromagnetic wave absorber includes: a first layer having a first enclosing layer that encloses an electromagnetic wave radiator, and a first metal film formed on the first enclosing layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10615788
    Abstract: A protective circuit includes a first capacitance element and a second capacitance element. A first capacitance value of the first capacitance element increases with an increase in a voltage applied to a first terminal of a circuit element. The second capacitance element is connected in series with the first capacitance element between the first terminal and a second terminal which is a reference potential terminal. The second capacitance element has a second fixed capacitance value which is larger than the first capacitance value until the voltage reaches a first value. The second capacitance element has a breakdown voltage characteristic higher than a breakdown voltage characteristic of the circuit element.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 7, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Publication number: 20200075740
    Abstract: An amplifying device includes: a comb-shaped transistor that includes a comb-shaped source electrode having a plurality of source fingers; one or more resistors connected between the source electrode and a ground; and a plurality of capacitors connected between the source electrode and the ground, wherein the capacitors are separated from each other and arranged in a direction in which the source fingers are arranged.
    Type: Application
    Filed: August 23, 2019
    Publication date: March 5, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Masato Nishimori, Ikuo Soga, Tatsuya Hirose, Yoichi Kawano
  • Patent number: 10577992
    Abstract: A disclosed microwave heating apparatus includes a casing part configured to accommodate an object to be heated; a microwave generator configured to generate a microwave; an electromagnetic wave generator configured to generate an electromagnetic wave whose frequency is different from that of the microwave; an electromagnetic wave sensor configured to measure power of the electromagnetic wave, the power of the electromagnetic wave being measured after the electromagnetic wave incident on the casing part from the electromagnetic wave generator has passed through the object to be heated; and a controller configured to control, based on the power measured in the electromagnetic wave sensor, the microwave generator to generate the microwave.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: March 3, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Tadahiro Imada, Katsusada Motoyoshi, Tatsuya Hirose, Yoichi Kawano
  • Patent number: 10526943
    Abstract: A disclosed microwave heating apparatus includes a casing part configured to accommodate an object to be heated; a microwave generator configured to generate a microwave; an electromagnetic wave generator configured to generate an electromagnetic wave whose frequency is different from that of the microwave; an electromagnetic wave sensor configured to measure power of the electromagnetic wave, the power of the electromagnetic wave being measured after the electromagnetic wave incident on the casing part from the electromagnetic wave generator has passed through the object to be heated; and a controller configured to control, based on the power measured in the electromagnetic wave sensor, the microwave generator to generate the microwave.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 7, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Tadahiro Imada, Katsusada Motoyoshi, Tatsuya Hirose, Yoichi Kawano
  • Patent number: 10447141
    Abstract: A waveform shaping circuit includes a first parallel circuit including a first capacitance element and a first resistance element coupled in parallel with each other, a positive pulse voltage being applied to a first terminal of the first capacitance element and a second terminal of the first resistance element, a first rectifier circuit disposed between a point of coupling between a third terminal of the first capacitance element and a fourth terminal of the first resistance element and an output terminal.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10444273
    Abstract: A partial discharge measurement device includes: an impulse voltage application unit; a measurement control unit; and first and second partial discharge detection unit. The measurement control unit includes: a first and a second detector level partial discharge counting unit; and a partial discharge resistance evaluation unit. Each of the first and the second detector level partial discharge counting units outputs a first or second detection signal when the first or second detection signal exceeds a predetermined specified value. The partial discharge resistance evaluation unit counts the number of occurrences of partial discharge based on an output from the first and second detector level partial discharge counting unit, and regards the impulse voltage value at which the count value has reached a predetermined value as a partial discharge inception voltage under the repeated impulse voltage application.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: October 15, 2019
    Assignees: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION, KABUSHIKI KAISHA TOSHIBA, TOSHIBA INDUSTRIAL PRODUCTS AND SYSTEMS CORPORATION
    Inventors: Tomomi Ikegami, Tetsuo Yoshimitsu, Takayuki Sakurai, Tatsuya Hirose, Satoshi Hiroshima, Yuji Yamamoto
  • Patent number: 10432081
    Abstract: A waveform shaping circuit includes a first parallel circuit including a first capacitance element and a first resistance element coupled in parallel with each other, a positive pulse voltage being applied to a first terminal of the first capacitance element and a second terminal of the first resistance element, a gate terminal of a field-effect transistor being electrically coupled to a third terminal of the first capacitance element and a fourth terminal of the first resistance element, a first Zener diode having a first anode coupled to the third terminal and the fourth terminal, and a second parallel circuit including a second capacitance element and a second resistance element coupled in parallel with each other, a first cathode of the first Zener diode being coupled to a fifth terminal of the second capacitance element and a sixth terminal of the second resistance element.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: October 1, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Publication number: 20190296632
    Abstract: A waveform shaping circuit includes a first variable gate voltage circuit that controls a minimum voltage of a pulse voltage based on a drain current or a source current of a field effect transistor, the pulse voltage having a positive or negative value and being applied to a gate of the field effect transistor, and a second variable gate voltage circuit that controls a maximum voltage of the pulse voltage based on the drain current or the source current.
    Type: Application
    Filed: January 16, 2019
    Publication date: September 26, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10381941
    Abstract: A switching power supply device includes a transformer including a primary winding and a secondary winding, a first transistor coupled to the primary winding, a first control circuit that outputs a first control voltage, a delay circuit that delays the first control voltage and supplies the delayed first control voltage to the first transistor, a second transistor that has a first terminal coupled to the secondary winding, a diode coupled to the secondary winding, a second control circuit that outputs a third control voltage used for controlling a switching operation of the second transistor, a control voltage generation circuit that generates the second control voltage, and a delay time control circuit that determines an ON period in which the diode is switched on and controls a delay time so that the delay time by which the delay circuit delays the first control voltage is shorter for a longer ON period.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: August 13, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Publication number: 20190229606
    Abstract: A gate driving circuit includes a first transistor, a first control circuit that changes a gate voltage of the first transistor from a low level to a high level, and a second control circuit that changes the gate voltage of the first transistor from the high level to the low level, wherein the first control circuit and the second control circuit are coupled to each other in parallel with respect to a gate of the first transistor.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Publication number: 20190229605
    Abstract: A waveform shaping circuit includes a first parallel circuit including a first capacitance element and a first resistance element coupled in parallel with each other, a positive pulse voltage being applied to a first terminal of the first capacitance element and a second terminal of the first resistance element, a gate terminal of a field-effect transistor being electrically coupled to a third terminal of the first capacitance element and a fourth terminal of the first resistance element, a first Zener diode having a first anode coupled to the third terminal and the fourth terminal, and a second parallel circuit including a second capacitance element and a second resistance element coupled in parallel with each other, a first cathode of the first Zener diode being coupled to a fifth terminal of the second capacitance element and a sixth terminal of the second resistance element.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 25, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Publication number: 20190229604
    Abstract: A waveform shaping circuit includes a first parallel circuit including a first capacitance element and a first resistance element coupled in parallel with each other, a positive pulse voltage being applied to a first terminal of the first capacitance element and a second terminal of the first resistance element, a first rectifier circuit disposed between a point of coupling between a third terminal of the first capacitance element and a fourth terminal of the first resistance element and an output terminal.
    Type: Application
    Filed: December 18, 2018
    Publication date: July 25, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Publication number: 20190211735
    Abstract: A clogging determination device includes a first antenna disposed at one of a side of a first end and a side of a second end of a filter disposed internally of a case, a second antenna disposed at the other of the side of the first end and the side of the second end of the filter, a multi-tone signal generator that has an output terminal coupled to the first antenna, outputs from the output terminal a multi-tone signal obtained by compositing a plurality of signals having different frequencies, and moves a position of an envelope of the multi-tone signal emitted to the filter from the first antenna, a detector that is coupled to the second antenna, and detects an intensity of the multi-tone signal received by the second antenna, and a determinator that determines a degree of clogging of the filter based on an intensity of the multi-tone signal.
    Type: Application
    Filed: December 19, 2018
    Publication date: July 11, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Publication number: 20190207530
    Abstract: A power supply circuit includes a transformer that includes a primary winding and a first secondary winding, a first diode coupled to the first secondary winding in series, a first node, coupled to the primary winding, for receiving a supplied voltage, a second node coupled to a series connection circuit, the series connection circuit is including the first secondary winding and the first diode coupled to the first secondary winding in series, a first capacitor coupled to the second node, a first resistor coupled between the first node and the second node; and a driving circuit that includes a power supply terminal coupled to the second node.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 4, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuya Hirose