Abstract: An cable drive device (10) having a motor (M), a speed reducer (G), a nut member (26) connected to the speed reducer, a rod (32) screwed to the nut member (26) and guided by a guide member (34) so as not to rotate, a control cable (15) composed of an inner cable (45) connected to the rod and a guide tube (49) for guiding the inner cable, a sensor for detecting the amount of operation of the cable based on the amount of rotation of the speed reducer (G), and a load sensor (17) for detecting a load applied to the cable. An electric brake device can be obtained by connecting the control cable and a brake mechanism of the cable drive device (10).

Abstract: An cable drive device (10) having a motor (M), a speed reducer (G), a nut member (26) connected to the speed reducer, a rod (32) screwed to the nut member (26) and guided by a guide member (34) so as not to rotate, a control cable (15) composed of an inner cable (45) connected to the rod and a guide tube (49) for guiding the inner cable, a sensor for detecting the amount of operation of the cable based on the amount of rotation of the speed reducer (G), and a load sensor (17) for detecting a load applied to the cable. An electric brake device can be obtained by connecting the control cable and a brake mechanism of the cable drive device (10).

Abstract: An cable drive device (10) having a motor (M), a speed reducer (G), a nut member (26) connected to the speed reducer, a rod (32) screwed to the nut member (26) and guided by a guide member (34) so as not to rotate, a control cable (15) composed of an inner cable (45) connected to the rod and a guide tube (49) for guiding the inner cable, a sensor for detecting the amount of operation of the cable based on the amount of rotation of the speed reducer (G), and a load sensor (17) for detecting a load applied to the cable. An electric brake device can be obtained by connecting the control cable and a brake mechanism of the cable drive device (10).

Abstract: In a timer device, the counter thereof counts the number of the pulses of a pulse signal input from an external apparatus up to a count initial value to output a count ending signal at the time of the end of the counting, and the control signal generator thereof generates a signal for controlling the external apparatus on the count ending signal output from the counter, and further the count operation controller thereof controls the count operation of the counter on a state change signal indicating the change of the state of the external apparatus. Thereby, the timer device can execute extensive processing by means of few counters.

Abstract: An analog/digital converter has a register which stores data for selecting an analog voltage to be scanned from analog voltages of plural channels, another register which stores data for selecting an analog voltage to be temporarily scanned, and a counter which is set to count a predetermined number of scanning cycles of the analog voltages. In the converter, analog voltages of plural channels can adequately be scanned by a simple configuration, and, in the course of continuously conducting the scan operation, analog voltages of channels other than the currently scanned channels can temporarily be scanned, so that the analog voltages are converted into digital values.

Abstract: An address translating circuit is disclosed for translating a virtual address signal generated from an external CPU into a real address signal applicable to the dual-port random access memory (DPRAM) in the microcomputer. This address translating circuit includes an offset register, an enabling signal generating circuit, and a subtractor provided in the microcomputer. The offset data obtained based upon the difference between an address map handled by the external CPU and an address map handled by the internal CPU is set in the offset register. The enabling signal generating circuit is responsive to the more significant bits of the virtual address signal and the offset data to generate an enabling signal. The subtractor is responsive to the intermediate bits of the virtual address signal and the offset data to generate a translated address signal.