Abstract: Processors, data structures and methods for operating two or more processors over a network are disclosed. A processor can load, store and save information relating to the operation of one or more of its secondary processors in a unit of migration that includes either contents of exclusively associated memories of two or more secondary processors related to the execution state of a suspended process or contents of exclusively associated memories of one or more secondary processors related to the execution state of a suspended process and shared initialized data for the process. Such a unit of migration may be embodied in a processor readable medium.

Abstract: The present invention provides an interlayer film for a laminated glass which can suppress bubble formation and bubble growth in the laminated glass, and an interlayer film for the laminated glass. An interlayer film for a laminated glass 1 includes a first layer 2, a second layer laminated on one face 2a of the first layer 2. Each of the first layer 3 and the second layer 3 contains a polyvinyl acetal resin and a plasticizer. The hydroxyl content of the polyvinyl acetal resin in the first layer 2 is lower than the hydroxyl content of the polyvinyl acetal resin in the second layer 3. The difference between the hydroxyl content of the polyvinyl acetal resin in the first layer 2 and the hydroxyl content of the polyvinyl acetal resin in the second layer 3 is at most 9.2 mol %. If the difference in the content is higher than 8.5 mol % and at most 9.2 mol %, a degree of acetylation of the polyvinyl acetal resin of the polyvinyl acetal resin in the first layer is at most 8 mol %.

Abstract: The present invention provides an interlayer film for a laminated glass which has excellent sound insulation and can suppress bubble formation and bubble growth in the laminated glass, and a multilayer interlayer film for the laminated glass including the interlayer film for a laminated glass. An interlayer film for a laminated glass 2 includes a thermoplastic resin and a plasticizer. The ratio of a high molecular weight component with an absolute molecular weight of 1000000 or more in the thermoplastic resin is 7.4% or higher, or the ratio of a high molecular weight component with a polystyrene-equivalent molecular weight of 1000000 or more in the thermoplastic resin is 9% or higher. A first multilayer interlayer film 1 for a laminated glass includes an interlayer film 2 for a laminated glass and an interlayer film 3 for a laminated glass that contains a thermoplastic resin and a plasticizer, and is laminated on one face 2a of the interlayer film 2 for a laminated glass.

Abstract: The present invention provides an interlayer film for a laminated glass which can suppress bubble formation and bubble growth in the laminated glass. An interlayer film 1 for a laminated glass includes a first layer 2 and a second layer 3 laminated on one face 2a of the first layer 2. Each of the first layer 2 and the second layer 3 contains a polyvinyl acetal resin and a plasticizer. In the case of measuring viscoelasticity of a resin film (glass transition temperature: Tg (° C.)) formed from the first layer 2 or a resin film (glass transition temperature: Tg (° C.)) formed with 100 parts by weight of the polyvinyl acetal resin contained in the first layer 2 and 60 parts by weight of a plasticizer of triethylene glycol di-2-ethylhexanoate (3GO) , the resin film has an elastic modulus of G?(Tg+80) at (Tg+80)° C. and an elastic modulus of G?(Tg+30) at (Tg+30)° C., and provides a ratio (G?(Tg+80)/G?(Tg+30)) of 0.65 or higher.

Abstract: The present invention provides an interlayer film for a laminated glass which can suppress bubble formation and bubble growth in the laminated glass. An interlayer film 1 for a laminated glass includes a first layer 2 and a second layer 3 laminated on one face 2a of the first layer 2. Each of the first layer 2 and the second layer 3 contains a polyvinyl acetal resin and a plasticizer. The polyvinyl acetal resin in the first layer 2 is obtained by acetalizing a polyvinyl alcohol resin that has a degree of polymerization exceeding 3000.

Abstract: A system for interactive computer graphics enables generation of Bezier curves from a series of points based on the relative position of successive points in the series. For example, for successive points in a series, point A, point B, and point C are successive points in the series of points, and wherein a control point corresponding to point B and associated with the segment AB is determined by the equation B+RA*(RA*(B?C)+RC*(A?B)), and a control point corresponding to point B and associated with the segment BC is determined by the equation PBBC=B+RC*(RA*(C?B)+RC*(B?A)), where RA=|AB|/(|AB|+|BC|), and RC=|BC|/(|AB|+|BC|).

Abstract: Secure operation of processors is disclosed. A cell processor receives a secure file image from a client device at a processor of a host device (host cell processor), wherein the secure file image includes encrypted contents.

Abstract: A nuclear reactor fueling plan evaluating system and method in which reactor shutdown margin evaluation are performed quickly and accurately. A fueling procedure formulating part and an input setting part having databases are included. A maximum worth control rod candidate selecting part having a control rod worth calculating means which inputs fuel loading and control rod patterns of each fueling act, inputs a relatively simple second physics model, calculates control rod worth from the difference between the degree of subcriticality of a reactor core in a state that all control rods are inserted and the degree of subcriticality of the reactor core in a state that a single control rod is withdrawn for each fueling step, and selects a determined number of maximum worth control rod candidates. A reactor shutdown margin calculating part inputs a subdivided first physics model and calculates reactor shutdown margin for each maximum worth control rod candidate.

Abstract: A system for interactive computer graphics enables generation of Bezier curves from a series of points based on the relative position of successive points in the series. For example, for successive points in a series, point A, point B, and point C are successive points in the series of points, and wherein a control point corresponding to point B and associated with the segment AB is determined by the equation B+RA*(RA*(B?C)+RC*(A?B)), and a control point corresponding to point B and associated with the segment BC is determined by the equation PBBC=B+RC*(RA*(C?B)+RC*(B?A)), where RA=|AB|/(|AB|+|BC|), and RC=|BC|/(|AB|+|BC|).

Abstract: Secure operation of processors is disclosed. A cell processor receives a secure file image from a client device at a processor of a host device (host cell processor), wherein the secure file image includes encrypted contents.

Abstract: In an attachment structure, a vehicle-mounted electronic device is attached to a receiving box using an adjusting member for adjusting a difference between an external dimension of the electronic device and a dimension of a receiving space of the receiving box for receiving the electronic device. The adjusting member has an insertion-coupling device for insertion-coupling the adjusting member and the electronic device, and a first catch-coupling device for catch-coupling the adjusting member and the receiving box. The first catch-coupling device is an appended claw-receiving part that corresponds to a flexible claw on the receiving box, and the direction of insertion-coupling of the insertion-coupling device and the direction of catch-coupling of the first catch-coupling device are different.

Abstract: Secure operation of cell processors is disclosed. A cell processor receives a secure file image from a client device at a cell processor of a host device (host cell processor), wherein the secure file image includes an encrypted SPU image.

Abstract: Methods and apparatus provide for allocating a first stack module in response to a first function call of a software program running on a processing system; and allocating a second stack module in response to a second function call of the software program, wherein the second stack module is non-contiguous with respect to the first stack module.

Abstract: Methods and apparatus are provided for managing processor tasks in a multi-processor computing system. The system is operable to store the processor tasks in a shared memory that may be accessed by a plurality of sub-processing units of the multi-processor computing system; and permit the sub-processing units to determine which of the processor tasks should be copied from the shared memory and executed based on priorities of the processor tasks.

Abstract: Methods and apparatus are provided for executing processor tasks on a multi-processing system. The multi-processing system includes a plurality of sub-processing units and a main processing unit that may access a shared memory. Each sub-processing unit includes an on-chip local memory separate from the shared memory. The methods and apparatus contemplate: providing that the processor tasks be copied from the shared memory into the local memory of the sub-processing units in order to execute them, and prohibiting the execution of the processor tasks from the shared memory; and migrating at least one processor task from one of the sub-processing units to another of the sub-processing units.

Abstract: Methods and apparatus are provided for enhanced instruction handling in processing environments. A program reference may be associated with one or more program modules. The program modules may be loaded into local memory and information, such as code or data, may be obtained from the program modules based on the program reference. New program modules can be formed based on existing program modules. Generating direct references within a program module and avoiding indirect references between program modules can optimize the new program modules. A program module may be preloaded in the local memory based upon an insertion point. The insertion point can be determined statistically. The invention is particularly beneficial for multiprocessor systems having limited amounts of memory.

Abstract: Methods and systems are provided whereby, in one aspect, pointers to address locations of instructions, static data and dynamically-created data are stored such that the instructions, static data and dynamically-created data can be moved to a different memory or processor without changing the values of the pointers.

Abstract: Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address containing a primitive is divided into a parity byte and two or more portions, wherein the parity byte includes at least one bit. A value of the parity byte determines which of the two or more portions is a valid portion and which of them is an invalid portion. The primitive is of a memory size that is larger than a maximum size for atomic operation with the PPE and less than or equal to a maximum size for atomic operation with the SPE. Read with reservation and conditional write instructions are used by both the PPE and SPE to access or update a value of the atomic.

Abstract: Direct memory access is provided for each member of a group of IO devices organized into groups. Direct memory access for each IO device is performed in a predetermined order based on the predetermined groups, and may be completed by notification by an interrupt request. A predetermined time delay may be specified between each memory access by each IO device of a predetermined group.

Abstract: Task scheduling in a processing system having a main memory and a processor having a plurality of software-configurable registers is disclosed. The processor may be a synergistic processing unit (SPU) of a cell processor. The processing system operates under the control of a kernel and a program code. A subset of the plurality of software-configurable registers is reserved for use by the kernel. Upon occurrence of an interrupt event requiring control of the processor by the kernel, the kernel may be run on the processor without saving the contents the plurality of registers.