Patents by Inventor Tatsuya Kajita
Tatsuya Kajita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080265309Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.Type: ApplicationFiled: June 20, 2008Publication date: October 30, 2008Applicant: SPANSION LLCInventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Patent number: 7410857Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.Type: GrantFiled: July 23, 2007Date of Patent: August 12, 2008Assignee: Spansion LLC.Inventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20070262374Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.Type: ApplicationFiled: July 23, 2007Publication date: November 15, 2007Applicant: SPANSION LLCInventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Patent number: 7253046Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.Type: GrantFiled: February 25, 2005Date of Patent: August 7, 2007Assignee: Spansion LLC.Inventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20060228899Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: ApplicationFiled: May 26, 2006Publication date: October 12, 2006Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Patent number: 7098147Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: GrantFiled: August 20, 2003Date of Patent: August 29, 2006Assignee: Fujitsu Amd Semiconductor LimitedInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20050224866Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.Type: ApplicationFiled: February 25, 2005Publication date: October 13, 2005Applicant: FASL LLCInventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20050212074Abstract: A trench (4) is formed in a semiconductor substrate (1), and then a plasma oxynitride film (5) is formed on a side wall surface and a bottom surface of the trench (4) at a temperature of approximately 300° C. to 650° C. At such a temperature, no outward diffusion of impurities from the semiconductor substrate (1) occurs. Therefore, any problems such as formation of a parasitic transistor hardly occur even when ions of impurities are not implanted thereafter. After the plasma oxynitride film (5) is formed, it is thermally oxidized, and a portion where the outermost surface of the semiconductor substrate (1) meets the wall surface of the trench (4) is turned into a curved surface. As a result, the outermost surface of the semiconductor substrate (1) and the wall surface of the trench (4) meet each other while forming a curved surface, and hence a parasitic transistor is hardly formed at this portion. Consequently, formation of a hump is prevented, thereby achieving favorable characteristics.Type: ApplicationFiled: February 25, 2005Publication date: September 29, 2005Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Kentaro Sera, Hiroyuki Nansei, Manabu Nakamura, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20050212035Abstract: Tunnel insulating films (3) are formed in element regions demarcated by element isolation insulating films (2). Thereafter, for each memory cell, a floating gate (4) is formed, and an ONO film (5) and a control gate (6) are further formed. Next, a plasma insulating film (7) is formed on surfaces of stacked gates. The plasma insulating film is immune to plane orientation of a base film. Therefore, the entire plasma insulating film (7) has a substantially uniform thickness, and consequently, even if the maximum thickness thereof is not as large as that of a thermal oxide film, hydrogen entrance is prevented when the interlayer insulating film is thereafter formed, and electron leakage is also prevented. The reduction in thickness of this insulating film makes it possible to reduce birds' beaks, and efficiency in erase/write of data can be enhanced.Type: ApplicationFiled: February 25, 2005Publication date: September 29, 2005Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Yukihiro Utsuno, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Hiroyuki Nansei, Hideo Takagi, Tatsuya Kajita
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Publication number: 20040082198Abstract: A chemical oxide film formed on a semiconductor substrate is formed by wet cleaning using a strongly acidic solution so that the adhesion of impurities to the chemical oxide film can be reduced between a wet cleaning process and an insulation film forming process. This makes it possible to prevent insulation degradation of a gate insulation film when the gate insulation film embracing the chemical oxide film is formed in the insulation film forming process in which low-temperature processing is conducted.Type: ApplicationFiled: September 11, 2003Publication date: April 29, 2004Inventors: Manabu Nakamura, Hiroyuki Nansei, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20040043638Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: ApplicationFiled: August 20, 2003Publication date: March 4, 2004Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Patent number: 6444530Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.Type: GrantFiled: May 25, 1999Date of Patent: September 3, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Hung-Sheng Chen, Unsoon Kim, Yu Sun, Chi Chang, Mark Ramsbey, Mark Randolph, Tatsuya Kajita, Angela Hui, Fei Wang, Mark Chang
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Patent number: 6444539Abstract: A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads.Type: GrantFiled: February 15, 2001Date of Patent: September 3, 2002Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark Chang, Chi Chang, Hung-Sheng Chen
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Patent number: 6420224Abstract: A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have traditionally covered the alignment marks with layers of oxide material.Type: GrantFiled: April 16, 2001Date of Patent: July 16, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Tatsuya Kajita, Mark S. Chang
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Publication number: 20010022405Abstract: A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have traditionally covered the alignment marks with layers of oxide material.Type: ApplicationFiled: April 16, 2001Publication date: September 20, 2001Inventors: Tatsuya Kajita, Mark S. Chang
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Patent number: 6249036Abstract: A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have traditionally covered the alignment marks with layers of oxide material.Type: GrantFiled: March 18, 1998Date of Patent: June 19, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Tatsuya Kajita, Mark S. Chang
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Patent number: 6232646Abstract: A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads.Type: GrantFiled: May 20, 1998Date of Patent: May 15, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark Chang, Chi Chang, Hung-Sheng Chen
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Patent number: 6014329Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.Type: GrantFiled: December 5, 1997Date of Patent: January 11, 2000Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Takao Akaogi, Yasushige Ogawa, Tatsuya Kajita, Hisayoshi Watanabe, Minoru Yamashita
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Patent number: 5950086Abstract: A semiconductor device is fabricated by the step of forming a first device isolation film in a peripheral circuit region by the use of a first pattern and a second device isolation film in a memory cell region by the use of a second pattern; forming a first conducting film processed by the use of a third pattern having a pattern-to-be-removed in a peripheral edge of the memory cell region; the step of forming an insulation film covering the memory cell region and processed by the use of a fourth pattern whose peripheral edge is positioned on the pattern-to-be-removed of the third pattern; and the step of forming a second conducting film processed by a fifth pattern.Type: GrantFiled: June 18, 1997Date of Patent: September 7, 1999Assignee: Fujitsu LimitedInventors: Satoshi Takahashi, Tatsuya Kajita, Hideo Kurihara, Hideki Komori, Masaaki Higashitani
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Patent number: 5910916Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.Type: GrantFiled: December 5, 1997Date of Patent: June 8, 1999Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Takao Akaogi, Yasushige Ogawa, Tatsuya Kajita, Hisayoshi Watanabe, Minoru Yamashita