Patents by Inventor Tatsuya Kamei

Tatsuya Kamei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10915393
    Abstract: Existing semiconductor devices cannot detect a failure occurring in a circuit required for mode switching processing for other than arithmetic cores, so that reliability is inadequate. A semiconductor device of an embodiment of the invention includes: a selector which is provided corresponding to among plural arithmetic cores one used as a checking arithmetic core in lock-step mode and which, in lock-step mode, blocks the interface signals outputted from the corresponding arithmetic core and, in split mode, lets the interface signals outputted from the corresponding arithmetic core through; an access monitor which monitors the interface signals outputted via a selector and, when an abnormal state of the interface signals is detected, outputs an error signal; and an error control unit which outputs, based on the error signal outputted from the access monitor, an abnormal state processing request to a higher-order system.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 9, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akihiro Yamate, Yoshitaka Taki, Tatsuya Kamei, Yoichi Yuyama
  • Patent number: 10540182
    Abstract: In a processor including an instruction prefetch buffer to prefetch a group of instructions with continuous addresses from a memory, the probability of occurrence of the situation where a bus is occupied by the instruction prefetch more than necessary is reduced. The processor includes an instruction fetch address generator which controls the address and amount of the instruction to be prefetched to the instruction prefetch buffer. The instruction fetch address generator includes a table which stores an instruction prefetch amount of an instruction to make the instruction prefetch buffer perform prefetching in association with a branch destination address of a branch arising in the process execution unit. When a branch arises in the process execution unit, the instruction fetch address generator makes an instruction prefetch buffer prefetch the instruction of the instruction prefetch amount corresponding to the branch destination address concerned including the branch destination address of the arisen branch.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hajime Yamashita, Tatsuya Kamei
  • Publication number: 20190155680
    Abstract: Existing semiconductor devices cannot detect a failure occurring in a circuit required for mode switching processing for other than arithmetic cores, so that reliability is inadequate. A semiconductor device of an embodiment of the invention includes: a selector which is provided corresponding to among plural arithmetic cores one used as a checking arithmetic core in lock-step mode and which, in lock-step mode, blocks the interface signals outputted from the corresponding arithmetic core and, in split mode, lets the interface signals outputted from the corresponding arithmetic core through; an access monitor which monitors the interface signals outputted via a selector and, when an abnormal state of the interface signals is detected, outputs an error signal; and an error control unit which outputs, based on the error signal outputted from the access monitor, an abnormal state processing request to a higher-order system.
    Type: Application
    Filed: September 11, 2018
    Publication date: May 23, 2019
    Inventors: Akihiro YAMATE, Yoshitaka TAKI, Tatsuya KAMEI, Yoichi YUYAMA
  • Publication number: 20180196675
    Abstract: In a processor including an instruction prefetch buffer to prefetch a group of instructions with continuous addresses from a memory, the probability of occurrence of the situation where a bus is occupied by the instruction prefetch more than necessary is reduced. The processor includes an instruction fetch address generator which controls the address and amount of the instruction to be prefetched to the instruction prefetch buffer. The instruction fetch address generator includes a table which stores an instruction prefetch amount of an instruction to make the instruction prefetch buffer perform prefetching in association with a branch destination address of a branch arising in the process execution unit. When a branch arises in the process execution unit, the instruction fetch address generator makes an instruction prefetch buffer prefetch the instruction of the instruction prefetch amount corresponding to the branch destination address concerned including the branch destination address of the arisen branch.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: Hajime YAMASHITA, Tatsuya KAMEI
  • Patent number: 9946546
    Abstract: In a processor including an instruction prefetch buffer to prefetch a group of instructions with continuous addresses from a memory, the probability of occurrence of the situation where a bus is occupied by the instruction prefetch more than necessary is reduced. The processor includes an instruction fetch address generator which controls the address and amount of the instruction to be prefetched to the instruction prefetch buffer. The instruction fetch address generator includes a table which stores an instruction prefetch amount of an instruction to make the instruction prefetch buffer perform prefetching in association with a branch destination address of a branch arising in the process execution unit. When a branch arises in the process execution unit, the instruction fetch address generator makes an instruction prefetch buffer prefetch the instruction of the instruction prefetch amount corresponding to the branch destination address concerned including the branch destination address of the arisen branch.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hajime Yamashita, Tatsuya Kamei
  • Publication number: 20160253178
    Abstract: In a processor including an instruction prefetch buffer to prefetch a group of instructions with continuous addresses from a memory, the probability of occurrence of the situation where a bus is occupied by the instruction prefetch more than necessary is reduced. The processor includes an instruction fetch address generator which controls the address and amount of the instruction to be prefetched to the instruction prefetch buffer. The instruction fetch address generator includes a table which stores an instruction prefetch amount of an instruction to make the instruction prefetch buffer perform prefetching in association with a branch destination address of a branch arising in the process execution unit. When a branch arises in the process execution unit, the instruction fetch address generator makes an instruction prefetch buffer prefetch the instruction of the instruction prefetch amount corresponding to the branch destination address concerned including the branch destination address of the arisen branch.
    Type: Application
    Filed: February 25, 2016
    Publication date: September 1, 2016
    Inventors: Hajime YAMASHITA, Tatsuya KAMEI
  • Patent number: 8694705
    Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holding unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hirotaka Hara, Tatsuya Kamei, Takahiro Irita
  • Patent number: 8200934
    Abstract: To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: June 12, 2012
    Assignees: Hitachi, Ltd., Renesas Electronics Corporation, Waseda University
    Inventors: Hironori Kasahara, Keiji Kimura, Takashi Todaka, Tatsuya Kamei, Toshihiro Hattori
  • Patent number: 8108660
    Abstract: Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: January 31, 2012
    Assignees: Renesas Electronics Corporation, Waseda University
    Inventors: Hironori Kasahara, Keiji Kimura, Masayuki Ito, Tatsuya Kamei, Toshihiro Hattori
  • Publication number: 20110320660
    Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holing unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 29, 2011
    Inventors: Hirotaka HARA, Tatsuya Kamei, Takahiro Irita
  • Publication number: 20090193228
    Abstract: Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 30, 2009
    Inventors: Hironori KASAHARA, Keiji KIMURA, Masayuki ITO, Tatsuya KAMEI, Toshihiro HATTORI
  • Publication number: 20080270707
    Abstract: A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory (25,26). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.
    Type: Application
    Filed: June 24, 2008
    Publication date: October 30, 2008
    Inventors: Tatsuya Kamei, Masayuki Ito
  • Patent number: 7415576
    Abstract: A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory (25,26). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 19, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuya Kamei, Masayuki Ito
  • Publication number: 20080086617
    Abstract: To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.
    Type: Application
    Filed: October 1, 2007
    Publication date: April 10, 2008
    Inventors: Hironori KASAHARA, Keiji Kimura, Takashi Todaka, Tatsuya Kamei, Toshihiro Hattori
  • Patent number: 7356649
    Abstract: A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: April 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuki Kondoh, Tatsuya Kamei, Makoto Ishikawa
  • Publication number: 20060143405
    Abstract: A data processor has a central processing unit and a plurality of logical blocks (1104) to be connected to the central processing unit, and the central processing unit sets a predetermined logical block to be a control object based on a result of decode of a predetermined instruction code (CBP) and a function of the predetermined logical block is selected based on the result of decode of the predetermined instruction code and a part of address information which is incidental to the predetermined instruction code (TAG [14:13]). It is possible to decide an operating object in an early stage before reaching a memory access stage of a pipeline without requiring to allocate the instruction code in a one-to-one correspondence for the operation of the predetermined logical block.
    Type: Application
    Filed: December 23, 2005
    Publication date: June 29, 2006
    Inventors: Makoto Ishikawa, Tatsuya Kamei
  • Patent number: 7013415
    Abstract: A semiconductor integrated circuit which is provided with a shift scan path incorporated in each function module and a testing I/O terminal connected to a shift scan path and provided separately from a normal-operation-use I/O terminal, and which comprises, all formed on one semiconductor chip, a bus interface circuit for connecting normal-operation-use I/O terminals of a plurality of function modules to a bus, an external interface switching circuit which switches between the bus-side I/O terminal of the bus interface circuit and the testing I/O terminal of each function module for connection to an external terminal and an interface control circuit for switch-controlling the external interface switching circuit.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: March 14, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tatsuya Kamei, Junichi Nishimoto, Ken Tatezawa
  • Publication number: 20050257011
    Abstract: A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.
    Type: Application
    Filed: September 30, 2002
    Publication date: November 17, 2005
    Inventors: Yuki Kondoh, Tatsuya Kamei, Makoto Ishikawa
  • Publication number: 20050172049
    Abstract: A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory (25,26). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.
    Type: Application
    Filed: September 30, 2002
    Publication date: August 4, 2005
    Inventors: Tatsuya Kamei, Masayuki Ito
  • Patent number: 5672897
    Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 30, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Watanabe, Takahide Ikeda, Kiyoshi Tsukuda, Mitsuru Hirao, Touji Mukai, Tatsuya Kamei